Lines Matching refs:g3
716 ldstub [%o0 + SFMMU_CTX_LOCK], %g3 ! %g3 = per process (PP) lock
718 brz %g3, 5f
721 brnz,a,pt %g3, 4b ! spin if lock is 1
722 ldub [%o0 + SFMMU_CTX_LOCK], %g3
724 ldstub [%o0 + SFMMU_CTX_LOCK], %g3 ! %g3 = PP lock
769 add %o3, MMU_CTX_CNUM, %g3
774 * %g3 = mmu cnum address
783 ld [%g3], %o1
799 ! %g3 = addr of mmu_ctxp->cnum
801 cas [%g3], %o1, %o5
804 ld [%g3], %o1
864 ldx [%o2], %g3 /* current */
868 cmp %g2, %g3 /* is modified = current? */
870 stx %g3, [%o0] /* update new original */
875 ldx [%o2], %g3 /* new current */
876 stx %g3, [%o0] /* save as new original */
878 mov %g3, %g1
885 ldx [%o2], %g3 /* current */
887 cmp %g3, %g2 /* is modified = current? */
1471 SETUP_TSB_ASI(%o3, %g3)
1578 TTETOPFN(%g1, %o1, sfmmu_ttetopfn_l1, %g2, %g3, %g4)
1732 mov T_INSTR_MMU_MISS, %g3
1735 mov T_INSTR_MMU_MISS, %g3
1737 mov T_DATA_PROT, %g3 /* arg2 = traptype */
1739 move %icc, T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1741 move %icc, T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1756 * g3.l = type
1757 * g3.h = 0
1773 mov T_INSTR_MMU_MISS, %g3
1776 mov T_INSTR_MMU_MISS, %g3
1778 mov T_DATA_PROT, %g3 /* arg2 = traptype */
1780 move %icc, T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1782 move %icc, T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1786 * g3 = type
1798 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g4, %g3)
1802 mov T_INSTR_MMU_MISS, %g3
1805 move %icc, T_DATA_MMU_MISS, %g3
1806 movne %icc, T_DATA_PROT, %g3
1810 /* g1 = TL0 handler, g2 = tagacc, g3 = trap type */
1852 sub %g5, 1, %g3
1853 wrpr %g3, %tl
1863 sub %g5, 1, %g3
1864 wrpr %g3, %tl
1943 GET_MMU_D_ADDR(%g3, /*scratch*/ %g4)
1944 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
1952 mov T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1954 * g2=tagacc g3.l=type g3.h=0
2424 * g3 - g7 = scratch registers
2435 or %g0, RUNTIME_PATCH, %g3 ! ktsb_szcode (hot patched)
2437 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
2442 RUNTIME_PATCH_SETX(%g3, %g6)
2443 /* %g3 = contents of ktsb4m_base or ktsb4m_pbase */
2447 GET_TSBE_POINTER(MMU_PAGESHIFT4M, %g3, %g7, %g6, %g5)
2448 ! %g3 = 4M tsb entry pointer, as TSB miss handler expects
2460 * g3 = faulting context (clobbered, currently not used)
2468 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3) /* get 2nd utsbreg */
2469 brlz,pt %g3, 9f /* check for 2nd TSB */
2472 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2473 /* %g3 = second TSB entry ptr now, %g2 preserved */
2478 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3)
2479 brlz,pt %g3, 9f /* check for 2nd TSB */
2482 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2483 /* %g3 = second TSB entry ptr now, %g2 preserved */
2486 mov -1, %g3 /* set second tsbe ptr to -1 */
2489 GET_2ND_TSBE_PTR(%g7, %g1, %g3, %g4, %g5, sfmmu_uprot)
2490 /* %g3 = second TSB entry ptr now, %g7 clobbered */
2508 * %g3 = faulting context id (used)
2513 brnz,pn %g3, tsb_tl0_noctxt
2530 srlx %g2, MMU_PAGESHIFT4M, %g3 ! use 4m virt-page as TSB index
2536 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2543 sllx %g3, 64-(TSB_START_SIZE + RUNTIME_PATCH), %g3
2544 srlx %g3, 64-(TSB_START_SIZE + TSB_ENTRY_SHIFT + RUNTIME_PATCH), %g3
2545 add %g4, %g3, %g3 ! %g3 = 4m tsbe ptr
2546 ldda [%g3]RUNTIME_PATCH, %g4 ! %g4 = tag, %g5 = data
2553 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2570 * %g3 = faulting context id (used)
2574 brnz,pn %g3, tsb_tl0_noctxt /* invalid context? */
2606 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2630 srlx %g2, MMU_PAGESHIFT4M, %g3
2640 sllx %g3, 64-(TSB_START_SIZE + RUNTIME_PATCH), %g3
2641 srlx %g3, 64-(TSB_START_SIZE + TSB_ENTRY_SHIFT + RUNTIME_PATCH), %g3
2644 * At this point %g3 is our index into the TSB.
2648 ldda [%g7 + %g3]RUNTIME_PATCH, %g4 ! %g4 = tag, %g5 = data
2654 add %g7, %g3, %g3 ! %g3 = kernel second TSB ptr
2657 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2678 * g3 = 4M-indexed secondary TSB pointer
2696 * g3 - g6 = scratch registers
2705 mov -1, %g3
2715 * g3 - g6 = scratch registers
2724 mov -1, %g3
2739 * g3 - g6 = scratch registers
2749 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2750 /* g1 = first TSB pointer, g3 = second TSB pointer */
2752 PROBE_2ND_ITSB(%g3, %g7)
2792 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3)
2793 brlz,pt %g3, 2f
2795 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2796 PROBE_2ND_ITSB(%g3, %g7, uitlb_4m_probefail)
2807 mov %g1, %g3 /* save tsb8k reg in %g3 */
2808 GET_1ST_TSBE_PTR(%g3, %g1, %g5, sfmmu_uitlb)
2811 mov %g3, %g7 /* copy tsb8k reg in %g7 */
2812 GET_2ND_TSBE_PTR(%g6, %g7, %g3, %g4, %g5, sfmmu_uitlb)
2813 /* g1 = first TSB pointer, g3 = second TSB pointer */
2815 PROBE_2ND_ITSB(%g3, %g7, isynth)
2852 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3)
2853 brlz,pt %g3, 1f
2855 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2856 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail)
2910 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3)
2911 brlz,pt %g3, 5f
2913 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2914 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail2)
2938 mov %g1, %g3
2944 * g3 = (potentially) second TSB entry ptr
2956 * g3 = second TSB ptr IFF ISM pred. (else don't care)
2969 * g3 = second TSB ptr IFF ISM pred. (else don't care)
2973 ldxa [%g0]ASI_DMMU_TSB_8K, %g3
2982 * g3 = 8K TSB pointer register
2988 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2989 /* %g2 is okay, no need to reload, %g3 = second tsbe ptr */
2991 mov %g3, %g7
2992 GET_2ND_TSBE_PTR(%g2, %g7, %g3, %g4, %g5, sfmmu_udtlb)
2993 /* %g2 clobbered, %g3 =second tsbe ptr */
2999 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail)
3015 * g3 = 4M TSB entry pointer; -1 if no 2nd TSB
3044 stn %g3, [%g6 + TSBMISS_TSBPTR4M] /* save 2ND tsb pointer */
3046 sllx %g2, TAGACC_CTX_LSHIFT, %g3
3047 brz,a,pn %g3, 1f /* skip ahead if kernel */
3049 srlx %g3, TAGACC_CTX_LSHIFT, %g3 /* g3 = ctxnum */
3054 cmp %g3, INVALID_CONTEXT
3064 ISM_CHECK(%g2, %g6, %g3, %g4, %g5, %g7, %g1, tsb_l1, tsb_ism)
3068 * %g1 %g3, %g4, %g5, %g7 all clobbered
3082 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3111 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3128 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3149 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3167 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3176 * g3 = tte
3181 brlz,a,pt %g3, tsb_validtte
3202 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3217 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3231 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3246 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3261 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3268 brgez,pn %g3, tsb_pagefault
3272 * g3 = tte
3289 * g3 = tte
3302 TTE_SET_REFMOD_ML(%g3, %g4, %g6, %g7, %g5, tsb_lset_refmod,
3322 andcc %g3, TTE_EXECPRM_INT, %g0 /* check execute bit is set */
3325 andcc %g3, TTE_EXECPRM_INT, %g0 /* check execute bit is set */
3334 TTE_SET_REF_ML(%g3, %g4, %g6, %g7, %g5, tsb_lset_ref)
3338 * g3 = tte
3375 and %g3, TTE_SZ_BITS, %g7 ! assumes TTE_SZ_SHFT is 0
3377 srlx %g3, TTE_SZ_SHFT, %g7
3388 srlx %g3, TTE_SZ2_SHFT, %g7
3419 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l3)
3425 mov %g3, %g5
3429 mov %g3, %g5
3431 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3435 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3462 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l4)
3469 mov %g3, %g5
3473 mov %g3, %g5
3475 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3479 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3496 * g3 = tte
3505 andcc %g3, TTE_EXECPRM_INT, %g0 /* is execprm bit set */
3509 mov %g3, %g5
3513 GET_4M_PFN_OFF(%g3, %g6, %g5, %g7, 1) /* make 4M pfn offset */
3517 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l5) /* update TSB */
3519 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3527 GET_4M_PFN_OFF(%g3, %g6, %g5, %g7, 2) /* make 4M pfn offset */
3529 or %g5, %g3, %g5 /* add 4M bits to TTE */
3533 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l6) /* update TSB */
3536 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3563 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l7)
3568 mov %g3, %g5 ! trapstat wants TTE in %g5
3572 mov %g3, %g5 ! trapstat wants TTE in %g5
3573 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3577 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3588 * g3 = ismmap->ism_seg
3598 srlx %g3, %g4, %g3 /* clr size field */
3600 sllx %g3, %g4, %g3 /* g3 = ism vbase */
3603 sub %g1, %g3, %g2 /* g2 = offset in ISM seg */
3615 SAVE_CTX1(%g5, %g3, %g1, tsb_shctxl)
3643 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT32M,
3649 brlz,a,pt %g3, tsb_validtte
3662 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT256M,
3667 brlz,a,pt %g3, tsb_validtte
3674 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT4M,
3680 brlz,a,pt %g3, tsb_validtte
3688 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT64K,
3694 brlz,a,pt %g3, tsb_validtte
3737 add %sp, STACK_BIAS, %g3
3738 srlx %g3, MMU_PAGESHIFT, %g3
3740 cmp %g3, %g4
3773 GET_MMU_D_ADDR(%g3, %g4)
3774 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
3800 GET_MMU_D_ADDR(%g3, %g4)
3801 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
3828 GET_MMU_D_ADDR(%g3, %g4)
3829 stx %g3, [%g5 + CPUC_DTRACE_ILLVAL]
3850 ldx [%g2 + MMFSA_I_CTX], %g3
3853 ldx [%g2 + MMFSA_I_CTX], %g3
3854 ldx [%g2 + MMFSA_D_CTX], %g3
3859 ldxa [%g2]ASI_IMMU, %g3
3860 ldxa [%g2]ASI_DMMU, %g3
3861 2: sllx %g3, TAGACC_CTX_LSHIFT, %g3
3863 brz,a,pn %g3, ptl1_panic ! panic if called for kernel
3947 GET_TTE(%o0, %o4, %g1, %g2, %o5, %g4, %g6, %g5, %g3,
3957 * g3 = scratch
3964 TTETOPFN(%g1, %o0, vatopfn_l2, %g2, %g3, %g4)
4012 * g3 = tte va
4088 GET_TTE(%o0, %o4, %g3, %g4, %g1, %o5, %g6, %o1, %g5,
4094 * %g3 = tte
4097 brgez,a,pn %g3, 1f /* check if tte is invalid */
4099 TTETOPFN(%g3, %o0, kvaszc2pfn_l2, %g2, %g4, %g5)
4101 * g3 = pfn
4104 mov %g3, %o0
4197 * g3 = 4M kpm TSB entry pointer
4221 stx %g3, [%g6 + KPMTSBM_TSBPTR]
4229 and %g4, KPMTSBM_TLTSBM_FLAG, %g3
4231 brz,pn %g3, sfmmu_kpm_exception
4241 * g3 = clobbered
4247 ldub [%g6 + KPMTSBM_SZSHIFT], %g3
4249 srax %g4, %g3, %g2 /* which alias range (r) */
4260 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmp2m)
4261 cmp %g3, MSEG_NULLPTR_PA
4267 * g2=pfn g3=mseg_pa
4270 ldxa [%g3 + MEMSEG_KPM_PBASE]%asi, %g7
4278 * g2=pfn g3=mseg_pa g4=inx
4281 ldxa [%g3 + MEMSEG_KPM_NKPMPGS]%asi, %g5
4292 ldxa [%g3 + MEMSEG_KPM_PAGES]%asi, %g5 /* kpm_pages */
4297 * g2=pfn g3=mseg_pa g4=offset g5=kp g7=kpmp_table_sz
4307 * g2=pfn g3=mseg_pa g4=offset g5=hashinx
4309 ldxa [%g3 + MEMSEG_KPM_PAGESPA]%asi, %g1 /* kpm_pagespa */
4318 add %g4, %g5, %g3
4319 add %g3, KPMHLK_LOCK, %g3 /* hlck_pa */
4323 * g1=kp_pa g2=pfn g3=hlck_pa
4347 * g1=kp_pa g2=ttarget g3=hlck_pa g4=kpmtsbp4m g5=tte g6=kpmtsbm_area
4351 KPMLOCK_ENTER(%g3, %g7, kpmtsbmhdlr1, ASI_MEM)
4387 KPMLOCK_EXIT(%g3, ASI_MEM)
4411 /* g3=hlck_pa */
4412 KPMLOCK_EXIT(%g3, ASI_MEM)
4421 * g3 = 4M kpm TSB pointer
4467 * g3 = 4M kpm TSB pointer (not used)
4477 ldub [%g6 + KPMTSBM_SZSHIFT], %g3 /* g3 = kpm_size_shift */
4479 srax %g4, %g3, %g7 /* which alias range (r) */
4486 sllx %g7, %g3, %g5 /* g5 = r << kpm_size_shift */
4503 * g3 = clobbered
4520 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmsp2m)
4521 cmp %g3, MSEG_NULLPTR_PA
4527 * g2=pfn g3=mseg_pa g6=per-CPU kpm tsbmiss area
4529 ldxa [%g3 + MEMSEG_KPM_PBASE]%asi, %g7
4535 * g2=pfn g3=mseg_pa g4=inx g6=per-CPU tsbmiss area
4537 ldxa [%g3 + MEMSEG_KPM_NKPMPGS]%asi, %g5
4545 ldxa [%g3 + MEMSEG_KPM_SPAGES]%asi, %g5
4550 * g2=pfn g3=mseg_pa g4=inx g5=ksp
4561 * g2=pfn g3=mseg_pa g4=offset g5=hashinx
4564 ldxa [%g3 + MEMSEG_KPM_PAGESPA]%asi, %g1 /* kpm_spagespa */
4575 add %g4, %g5, %g3 /* hlck_pa */
4579 * g1=ksp_pa g2=pfn g3=hlck_pa
4593 * g1=ksp_pa g2=ttarget g3=hlck_pa g4=ktsbp g5=tte (non-cacheable)
4598 KPMLOCK_ENTER(%g3, %g7, kpmtsbsmlock, ASI_MEM)
4631 KPMLOCK_EXIT(%g3, ASI_MEM)
4655 /* g3=hlck_pa */
4656 KPMLOCK_EXIT(%g3, ASI_MEM)
4784 GET_MMU_D_PTAGACC_CTXTYPE(%g2, %g3) ! %g2 = ptagacc, %g3 = ctx type
4789 * %g3 = ctx (cannot be INVALID_CONTEXT)
4791 brnz,pt %g3, 8f ! check for user context
4796 * Get 8K and 4M TSB pointers in %g1 and %g3 and
4803 or %g0, RUNTIME_PATCH, %g3 ! ktsb_szcode (hot patched)
4805 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
4810 RUNTIME_PATCH_SETX(%g3, %g6) ! %g3 = contents of ktsb4m_pbase
4814 GET_TSBE_POINTER(MMU_PAGESHIFT4M, %g3, %g7, %g6, %g5)
4815 ! %g3 = 4M tsb entry pointer, as TSB miss handler expects
4823 * Get second TSB pointer (or NULL if no second TSB) in %g3
4829 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3) /* get 2nd utsbreg */
4830 brlz,pt %g3, sfmmu_tsb_miss_tt /* done if no 2nd TSB */
4833 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
4834 /* %g3 = second TSB entry ptr now, %g2 preserved */
4850 GET_MMU_I_PTAGACC_CTXTYPE(%g2, %g3)