Lines Matching refs:g1
572 PANIC_IF_INTR_DISABLED_PSTR(%o0, sfmmu_di_l0, %g1)
610 sethi %hi(ksfmmup), %g1
611 ldx [%g1 + %lo(ksfmmup)], %g1
612 cmp %g1, %o0
616 sethi %hi(panicstr), %g1 ! if kernel as, panic
617 ldx [%g1 + %lo(panicstr)], %g1
618 tst %g1
631 PANIC_IF_INTR_ENABLED_PSTR(sfmmu_ei_l1, %g1)
634 mov %o3, %g1 ! save sfmmu pri/sh flag in %g1
655 sethi %hi(panicstr), %g1 ! test if panicstr is already set
656 ldx [%g1 + %lo(panicstr)], %g1
657 tst %g1
831 * %g1 = sfmmu private/shared flag (0:private, 1:shared)
847 clr %g1
856 SET_SECCTX(%o1, %g1, %o4, %o5, alloc_ctx_lbl1)
865 ldx [%o0], %g1 /* original */
871 casx [%o2], %g1, %g2
872 cmp %g1, %g2
878 mov %g3, %g1
886 ldx [%o0], %g1 /* original */
891 casx [%o2], %g1, %g2
893 cmp %g1, %g2
903 ldx [%o0], %g1
905 stx %g1, [%o1]
1466 PANIC_IF_INTR_DISABLED_PSTR(%o5, sfmmu_di_l2, %g1)
1472 TSB_UPDATE(%o0, %o2, %o1, %g1, %g2, locked_tsb_l8)
1489 SETUP_TSB_ASI(%o2, %g1)
1490 TSB_INVALIDATE(%o0, %o1, %g1, %o2, %o3, unload_tsbe)
1507 PANIC_IF_INTR_DISABLED_PSTR(%o5, sfmmu_di_l3, %g1)
1518 mov %o0, %g1 ! %g1 = vaddr
1521 GET_KPM_TSBE_POINTER(%o2, %g2, %g1, %o3, %o4)
1522 /* %g2 = tsbep, %g1 clobbered */
1524 srlx %o0, TTARGET_VA_SHIFT, %g1; ! %g1 = tag target
1526 TSB_UPDATE(%g2, %o1, %g1, %o3, %o4, locked_tsb_l9)
1550 mov %o0, %g1 ! %g1 = vaddr
1553 GET_KPM_TSBE_POINTER(%o1, %g2, %g1, %o3, %o4)
1554 /* %g2 = tsbep, %g1 clobbered */
1556 srlx %o0, TTARGET_VA_SHIFT, %g1; ! %g1 = tag target
1558 TSB_INVALIDATE(%g2, %g1, %o3, %o4, %o1, kpm_tsbinval)
1577 ldx [%o0], %g1 /* read tte */
1578 TTETOPFN(%g1, %o1, sfmmu_ttetopfn_l1, %g2, %g3, %g4)
1580 * g1 = pfn
1583 mov %g1, %o0
1746 ld [%g4 + %lo(test_ptl1_panic)], %g1
1748 cmp %g1, %g0
1750 or %g0, PTL1_BAD_DEBUG, %g1
1759 sethi %hi(trap), %g1
1760 or %g1, %lo(trap), %g1
1788 sethi %hi(sfmmu_tsbmiss_exception), %g1
1789 or %g1, %lo(sfmmu_tsbmiss_exception), %g1
1808 sethi %hi(sfmmu_tsbmiss_suspended), %g1
1809 or %g1, %lo(sfmmu_tsbmiss_suspended), %g1
1810 /* g1 = TL0 handler, g2 = tagacc, g3 = trap type */
1820 rdpr %tpc, %g1
1829 mov PTL1_BAD_WTRAP, %g1
1834 cmp %g1, %g4
1838 cmp %g1, %g4
1841 set fault_rtt_fn1, %g1
1842 wrpr %g0, %g1, %tnpc
1847 ! already got it: rdpr %tpc, %g1
1857 wrpr %g1, %tpc
1874 cmp %g1, %g4
1878 cmp %g1, %g4
1881 andn %g1, WTRAP_ALIGN, %g1 /* 128 byte aligned */
1882 add %g1, WTRAP_FAULTOFF, %g1
1883 wrpr %g0, %g1, %tnpc
1901 mov PTL1_BAD_WTRAP, %g1
1904 mov PTL1_BAD_WTRAP, %g1
1913 CPU_PADDR(%g1, %g4)
1914 add %g1, CPU_TL1_HDLR, %g1
1915 lda [%g1]ASI_MEM, %g4
1917 sta %g0, [%g1]ASI_MEM
1919 mov PTL1_BAD_TRAP, %g1
1934 CPU_INDEX(%g1, %g2)
1936 sllx %g1, CPU_CORE_SHIFT, %g1
1937 add %g1, %g2, %g1
1938 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
1942 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
1944 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
1947 TSTAT_CHECK_TL1(1f, %g1, %g2)
1956 sethi %hi(trap), %g1
1957 or %g1, %lo(trap), %g1
2422 * g1 = tsb8k pointer register (clobbered)
2432 RUNTIME_PATCH_SETX(%g1, %g6)
2433 /* %g1 = contents of ktsb_base or ktsb_pbase */
2437 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
2438 ! %g1 = First TSB entry pointer, as TSB miss handler expects
2458 * g1 = tsb8k pointer register (ro)
2465 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2466 /* %g1 = first TSB entry ptr now, %g2 preserved */
2477 /* g1 = first TSB entry ptr */
2485 brgez,pt %g1, 9f /* check for 2nd TSB */
2489 GET_2ND_TSBE_PTR(%g7, %g1, %g3, %g4, %g5, sfmmu_uprot)
2491 mov %g1, %g7
2492 GET_1ST_TSBE_PTR(%g7, %g1, %g5, sfmmu_uprot)
2506 * %g1 = 8K TSB pointer register (not used, clobbered)
2524 iktsb: sllx %g2, 64-(TAGACC_SHIFT + TSB_START_SIZE + RUNTIME_PATCH), %g1
2525 srlx %g1, 64-(TSB_START_SIZE + TSB_ENTRY_SHIFT + RUNTIME_PATCH), %g1
2526 or %g4, %g1, %g1 ! form tsb ptr
2527 ldda [%g1]RUNTIME_PATCH, %g4 ! %g4 = tag, %g5 = data
2536 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2553 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2568 * %g1 = 8K TSB pointer register (not used, clobbered)
2592 dktsb: sllx %g2, 64-(TAGACC_SHIFT + TSB_START_SIZE + RUNTIME_PATCH), %g1
2593 srlx %g1, 64-(TSB_START_SIZE + TSB_ENTRY_SHIFT + RUNTIME_PATCH), %g1
2596 * At this point %g1 is our index into the TSB.
2600 ldda [%g7 + %g1]RUNTIME_PATCH, %g4 ! %g4 = tag, %g5 = data
2604 add %g7, %g1, %g1 /* form tsb ptr */
2606 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2627 * %g1 = 8K TSB pointer. Don't squash it.
2657 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2676 * g1 = 8K-indexed primary TSB pointer
2694 * g1 = tsb8k pointer register
2702 PROBE_1ST_ITSB(%g1, %g7, uitlb_fast_8k_probefail)
2713 * g1 = tsb8k pointer register
2721 PROBE_1ST_DTSB(%g1, %g7, udtlb_fast_8k_probefail)
2737 * g1 = tsb8k pointer register
2745 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2746 PROBE_1ST_ITSB(%g1, %g7, uitlb_8k_probefail)
2750 /* g1 = first TSB pointer, g3 = second TSB pointer */
2776 * g1 = tsb8k pointer register
2807 mov %g1, %g3 /* save tsb8k reg in %g3 */
2808 GET_1ST_TSBE_PTR(%g3, %g1, %g5, sfmmu_uitlb)
2809 PROBE_1ST_ITSB(%g1, %g7, uitlb_8k_probefail)
2813 /* g1 = first TSB pointer, g3 = second TSB pointer */
2833 * g1 = tsb8k pointer register
2884 * g1 = tsb8k pointer register
2917 PROBE_1ST_DTSB(%g1, %g7, udtlb_8k_first_probefail2)
2938 mov %g1, %g3
2942 * g1 = 8K TSB pointer register
2949 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2950 PROBE_1ST_DTSB(%g1, %g7, udtlb_first_probefail)
2954 * g1 = first TSB pointer
2961 mov %g1, %g4
2962 GET_1ST_TSBE_PTR(%g4, %g1, %g5, sfmmu_udtlb)
2963 PROBE_1ST_DTSB(%g1, %g7, udtlb_first_probefail)
2967 * g1 = first TSB pointer
2980 * g1 = First TSB entry ptr if !ISM pred, TSB8K ptr reg if ISM pred.
3013 * g1 = First TSB entry pointer
3043 stn %g1, [%g6 + TSBMISS_TSBPTR] /* save 1ST tsb pointer */
3064 ISM_CHECK(%g2, %g6, %g3, %g4, %g5, %g7, %g1, tsb_l1, tsb_ism)
3068 * %g1 %g3, %g4, %g5, %g7 all clobbered
3082 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3111 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3128 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3149 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3167 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3174 * g1 = hblk_misc
3202 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3217 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3231 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3246 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3261 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3271 * g1 = ctx1 flag
3278 brz,pt %g1, tsb_validtte
3280 ldub [%g6 + TSBMISS_URTTEFLAGS], %g1
3281 or %g1, HAT_CHKCTX1_FLAG, %g1
3282 stub %g1, [%g6 + TSBMISS_URTTEFLAGS]
3284 SAVE_CTX1(%g7, %g2, %g1, tsb_shmel)
3402 and %g7, HAT_CHKCTX1_FLAG, %g1
3403 brz,a,pn %g1, 1f
3404 ldn [%g6 + TSBMISS_TSBPTR], %g1 ! g1 = 1ST TSB ptr
3405 GET_UTSBREG_SHCTX(%g6, TSBMISS_TSBSCDPTR, %g1)
3406 brlz,a,pn %g1, ptl1_panic ! if no shared 3RD tsb
3407 mov PTL1_NO_SCDTSB8K, %g1 ! panic
3408 GET_3RD_TSBE_PTR(%g5, %g1, %g6, %g7)
3411 ldn [%g6 + TSBMISS_TSBPTR], %g1 ! g1 = 1ST TSB ptr
3419 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l3)
3431 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3435 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3442 and %g7, HAT_CHKCTX1_FLAG, %g1
3443 brz,a,pn %g1, 4f
3444 ldn [%g6 + TSBMISS_TSBPTR4M], %g1 ! g1 = 2ND TSB ptr
3445 GET_UTSBREG_SHCTX(%g6, TSBMISS_TSBSCDPTR4M, %g1)! g1 = 4TH TSB ptr
3446 brlz,a,pn %g1, 5f ! if no shared 4TH TSB
3448 GET_4TH_TSBE_PTR(%g5, %g1, %g6, %g7)
3451 ldn [%g6 + TSBMISS_TSBPTR4M], %g1 ! g1 = 2ND TSB ptr
3454 brlz,pn %g1, 5f /* Check to see if we have 2nd TSB programmed */
3462 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l4)
3475 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3479 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3507 ldn [%g6 + TSBMISS_TSBPTR4M], %g1 /* g1 = tsbp */
3508 brlz,a,pn %g1, 5f /* no 2nd tsb */
3517 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l5) /* update TSB */
3519 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3523 ldn [%g6 + TSBMISS_TSBPTR4M], %g1 /* g1 = 2ND TSB */
3528 brlz,a,pn %g1, 7f /* Check to see if we have 2nd TSB programmed */
3533 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l6) /* update TSB */
3536 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3550 ldn [%g6 + TSBMISS_TSBPTR], %g1 ! g1 = 8K TSB ptr
3554 ldn [%g6 + TSBMISS_TSBPTR4M], %g1 ! g1 = 4M TSB ptr
3555 brlz,pn %g1, 3f /* skip programming if 4M TSB ptr is -1 */
3563 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l7)
3573 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3577 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3594 mov PTL1_BAD_ISM, %g1
3599 set TAGACC_CTX_MASK, %g1 /* mask off ctx number */
3601 and %g2, %g1, %g4 /* g4 = ctx number */
3602 andn %g2, %g1, %g1 /* g1 = tlb miss vaddr */
3603 sub %g1, %g3, %g2 /* g2 = offset in ISM seg */
3615 SAVE_CTX1(%g5, %g3, %g1, tsb_shctxl)
3643 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT32M,
3657 mov PTL1_BAD_ISM, %g1
3662 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT256M,
3674 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT4M,
3688 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT64K,
3742 mov PTL1_BAD_STACK, %g1
3747 TSTAT_CHECK_TL1(2f, %g1, %g2)
3750 mov PTL1_BAD_KPROT_FAULT, %g1
3751 movne %icc, PTL1_BAD_KMISS, %g1
3764 CPU_INDEX(%g1, %g2)
3766 sllx %g1, CPU_CORE_SHIFT, %g1
3767 add %g1, %g2, %g1
3768 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
3772 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
3774 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
3781 TSTAT_CHECK_TL1(4f, %g1, %g2)
3791 CPU_INDEX(%g1, %g2)
3793 sllx %g1, CPU_CORE_SHIFT, %g1
3794 add %g1, %g2, %g1
3795 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
3799 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
3801 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
3811 mov PTL1_BAD_DTRACE_FLAGS, %g1
3839 mov PTL1_BAD_DTRACE_FLAGS, %g1
3840 TSTAT_CHECK_TL1(2f, %g1, %g2);
3864 mov PTL1_BAD_CTX_STEAL, %g1 ! since kernel ctx was stolen
3869 TSTAT_CHECK_TL1(sfmmu_mmu_trap, %g1, %g2)
3903 PANIC_IF_INTR_DISABLED_PSTR(%o3, sfmmu_di_l5, %g1)
3916 CPU_TSBMISS_AREA(%g1, %o5)
3917 ldn [%g1 + TSBMISS_KHATID], %o4
3921 mov %g1,%o5 /* o5 = tsbmiss_area */
3945 set TAGACC_CTX_MASK, %g1
3946 andn %o0, %g1, %o0
3947 GET_TTE(%o0, %o4, %g1, %g2, %o5, %g4, %g6, %g5, %g3,
3955 * g1 = tte
3961 brgez,a,pn %g1, 6f /* if tte invalid goto tl0 */
3963 stx %g1,[%o2] /* put tte into *ttep */
3964 TTETOPFN(%g1, %o0, vatopfn_l2, %g2, %g3, %g4)
3969 * g1 = pfn
3972 mov %g1, %o0
4010 * g1 = tte
4015 stx %g1,[%o2] /* put tte into *ttep */
4016 brgez,a,pn %g1, 8f /* if tte invalid goto 8: */
4059 PANIC_IF_INTR_DISABLED_PSTR(%o3, sfmmu_di_l6, %g1)
4067 CPU_TSBMISS_AREA(%g1, %o5)
4068 ldn [%g1 + TSBMISS_KHATID], %o4
4077 * %g1 = tsbmiss area
4088 GET_TTE(%o0, %o4, %g3, %g4, %g1, %o5, %g6, %o1, %g5,
4195 * g1 = 8K kpm TSB entry pointer
4239 * g1 = 8K kpm TSB pointer (not used)
4299 ldub [%g6 + KPMTSBM_KPMPSHIFT], %g1 /* kpmp_shift */
4301 srlx %g5, %g1, %g1 /* x = ksp >> kpmp_shift */
4302 add %g5, %g1, %g5 /* y = ksp + x */
4309 ldxa [%g3 + MEMSEG_KPM_PAGESPA]%asi, %g1 /* kpm_pagespa */
4310 add %g1, %g4, %g1 /* kp_pa */
4314 * g1=kp_refcntc_pa g2=pfn g5=hashinx
4323 * g1=kp_pa g2=pfn g3=hlck_pa
4347 * g1=kp_pa g2=ttarget g3=hlck_pa g4=kpmtsbp4m g5=tte g6=kpmtsbm_area
4354 ldsha [%g1 + KPMPAGE_REFCNTC]%asi, %g7 /* kp_refcntc */
4361 ldsha [%g1 + KPMPAGE_REFCNT]%asi, %g7
4368 mov ASI_N, %g1
4370 movnz %icc, ASI_MEM, %g1
4371 mov %g1, %asi
4379 TSB_LOCK_ENTRY(%g4, %g1, %g7, locked_tsb_l1)
4384 DTLB_STUFF(%g5, %g1, %g2, %g4, %g6)
4419 * g1 = 8K kpm TSB pointer
4447 stx %g1, [%g6 + KPMTSBM_TSBPTR] /* save 8K kpm TSB pointer */
4455 and %g4, KPMTSBM_TLTSBM_FLAG, %g1
4457 brz,pn %g1, sfmmu_kpm_exception
4465 * g1 = clobbered
4484 srlx %g2, MMU_PAGESHIFT, %g1 /* vaddr >> MMU_PAGESHIFT */
4485 and %g1, %g5, %g1 /* g1 = v */
4487 cmp %g7, %g1 /* if (r > v) */
4490 sub %g7, %g1, %g5 /* g5 = r - v */
4501 * g1 = vcolor (not used)
4553 ldub [%g6 + KPMTSBM_KPMPSHIFT], %g1 /* kpmp_shift */
4555 sllx %g5, %g1, %g1 /* x = ksp << kpmp_shift */
4556 add %g5, %g1, %g5 /* y = ksp + x */
4564 ldxa [%g3 + MEMSEG_KPM_PAGESPA]%asi, %g1 /* kpm_spagespa */
4565 add %g1, %g4, %g1 /* ksp_pa */
4570 * g1=ksp_pa g2=pfn g5=hashinx
4579 * g1=ksp_pa g2=pfn g3=hlck_pa
4593 * g1=ksp_pa g2=ttarget g3=hlck_pa g4=ktsbp g5=tte (non-cacheable)
4601 ldsba [%g1 + KPMSPAGE_MAPPED]%asi, %g7 /* kp_mapped */
4612 mov ASI_N, %g1
4614 movnz %icc, ASI_MEM, %g1
4615 mov %g1, %asi
4623 TSB_LOCK_ENTRY(%g4, %g1, %g7, locked_tsb_l2)
4796 * Get 8K and 4M TSB pointers in %g1 and %g3 and
4801 RUNTIME_PATCH_SETX(%g1, %g6) ! %g1 = contents of ktsb_pbase
4805 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
4806 ! %g1 = First TSB entry pointer, as TSB miss handler expects
4822 * Get first TSB pointer in %g1
4826 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
4827 /* %g1 = first TSB entry ptr now, %g2 preserved */