Lines Matching refs:C1
499 #define C1 C(1)
538 { 0xc4, 0x01, C0|C1|C2|C3, "PAPI_br_cn" }, /* br_inst_retired.conditional */ \
539 { 0x1d, 0x01, C0|C1|C2|C3, "PAPI_hw_int" }, /* hw_int.rcx */ \
540 { 0x17, 0x01, C0|C1|C2|C3, "PAPI_tot_iis" }, /* inst_queue_writes */ \
541 { 0x43, 0x01, C0|C1, "PAPI_l1_dca" }, /* l1d_all_ref.any */ \
542 { 0x24, 0x03, C0|C1|C2|C3, "PAPI_l1_dcm" }, /* l2_rqsts. loads and rfos */ \
543 { 0x40, 0x0f, C0|C1|C2|C3, "PAPI_l1_dcr" }, /* l1d_cache_ld.mesi */ \
544 { 0x41, 0x0f, C0|C1|C2|C3, "PAPI_l1_dcw" }, /* l1d_cache_st.mesi */ \
545 { 0x80, 0x03, C0|C1|C2|C3, "PAPI_l1_ica" }, /* l1i.reads */ \
546 { 0x80, 0x01, C0|C1|C2|C3, "PAPI_l1_ich" }, /* l1i.hits */ \
547 { 0x80, 0x02, C0|C1|C2|C3, "PAPI_l1_icm" }, /* l1i.misses */ \
548 { 0x80, 0x03, C0|C1|C2|C3, "PAPI_l1_icr" }, /* l1i.reads */ \
549 { 0x24, 0x33, C0|C1|C2|C3, "PAPI_l1_ldm" }, /* l2_rqsts. loads and ifetches */\
550 { 0x24, 0xff, C0|C1|C2|C3, "PAPI_l1_tcm" }, /* l2_rqsts.references */ \
551 { 0x24, 0x02, C0|C1|C2|C3, "PAPI_l2_ldm" }, /* l2_rqsts.ld_miss */ \
552 { 0x24, 0x08, C0|C1|C2|C3, "PAPI_l2_stm" }, /* l2_rqsts.rfo_miss */ \
553 { 0x24, 0x3f, C0|C1|C2|C3, "PAPI_l2_tca" }, \
555 { 0x24, 0x15, C0|C1|C2|C3, "PAPI_l2_tch" }, \
557 { 0x24, 0x2a, C0|C1|C2|C3, "PAPI_l2_tcm" }, \
559 { 0x24, 0x33, C0|C1|C2|C3, "PAPI_l2_tcr" }, /* l2_rqsts. loads and ifetches */\
560 { 0x24, 0x0c, C0|C1|C2|C3, "PAPI_l2_tcw" }, /* l2_rqsts.rfos */ \
561 { 0x2e, 0x4f, C0|C1|C2|C3, "PAPI_l3_tca" }, /* l3_lat_cache.reference */ \
562 { 0x2e, 0x41, C0|C1|C2|C3, "PAPI_l3_tcm" }, /* l3_lat_cache.misses */ \
563 { 0x0b, 0x01, C0|C1|C2|C3, "PAPI_ld_ins" }, /* mem_inst_retired.loads */ \
564 { 0x0b, 0x03, C0|C1|C2|C3, "PAPI_lst_ins" }, \
566 { 0x26, 0xf0, C0|C1|C2|C3, "PAPI_prf_dm" }, /* l2_data_rqsts.prefetch.mesi */ \
567 { 0x0b, 0x02, C0|C1|C2|C3, "PAPI_sr_ins" }, /* mem_inst_retired.stores */ \
568 { 0x49, 0x01, C0|C1|C2|C3, "PAPI_tlb_dm" }, /* dtlb_misses.any */ \
569 { 0x85, 0x01, C0|C1|C2|C3, "PAPI_tlb_im" } /* itlb_misses.any */
574 { 0x80, 0x04, C0|C1|C2|C3, "l1i.cycles_stalled" }, \
575 { 0x80, 0x01, C0|C1|C2|C3, "l1i.hits" }, \
576 { 0x80, 0x02, C0|C1|C2|C3, "l1i.misses" }, \
578 { 0x80, 0x03, C0|C1|C2|C3, "l1i.reads" }, \
579 { 0x82, 0x01, C0|C1|C2|C3, "large_itlb.hit" }, \
580 { 0x87, 0x0F, C0|C1|C2|C3, "ild_stall.any" }, \
582 { 0x87, 0x04, C0|C1|C2|C3, "ild_stall.iq_full" }, \
583 { 0x87, 0x01, C0|C1|C2|C3, "ild_stall.lcp" }, \
584 { 0x87, 0x02, C0|C1|C2|C3, "ild_stall.mru" }, \
586 { 0x87, 0x08, C0|C1|C2|C3, "ild_stall.regen" }, \
587 { 0xE6, 0x02, C0|C1|C2|C3, "baclear.bad_target" }, \
588 { 0xE6, 0x01, C0|C1|C2|C3, "baclear.clear" }, \
590 { 0xE8, 0x01, C0|C1|C2|C3, "bpu_clears.early" }, \
591 { 0xE8, 0x02, C0|C1|C2|C3, "bpu_clears.late" }, \
592 { 0xE5, 0x01, C0|C1|C2|C3, "bpu_missed_call_ret" }, \
594 { 0xE0, 0x01, C0|C1|C2|C3, "br_inst_decoded" }, \
595 { 0x88, 0x7F, C0|C1|C2|C3, "br_inst_exec.any" }, \
596 { 0x88, 0x01, C0|C1|C2|C3, "br_inst_exec.cond" }, \
598 { 0x88, 0x02, C0|C1|C2|C3, "br_inst_exec.direct" }, \
599 { 0x88, 0x10, C0|C1|C2|C3, "br_inst_exec.direct_near_call" }, \
600 { 0x88, 0x20, C0|C1|C2|C3, "br_inst_exec.indirect_near_call" }, \
602 { 0x88, 0x04, C0|C1|C2|C3, "br_inst_exec.indirect_non_call" }, \
603 { 0x88, 0x30, C0|C1|C2|C3, "br_inst_exec.near_calls" }, \
604 { 0x88, 0x07, C0|C1|C2|C3, "br_inst_exec.non_calls" }, \
606 { 0x88, 0x08, C0|C1|C2|C3, "br_inst_exec.return_near" }, \
607 { 0x88, 0x40, C0|C1|C2|C3, "br_inst_exec.taken" }, \
608 { 0x89, 0x7F, C0|C1|C2|C3, "br_misp_exec.any" }, \
610 { 0x89, 0x01, C0|C1|C2|C3, "br_misp_exec.cond" }, \
611 { 0x89, 0x02, C0|C1|C2|C3, "br_misp_exec.direct" }, \
612 { 0x89, 0x10, C0|C1|C2|C3, "br_misp_exec.direct_near_call" }, \
614 { 0x89, 0x20, C0|C1|C2|C3, "br_misp_exec.indirect_near_call" }, \
615 { 0x89, 0x04, C0|C1|C2|C3, "br_misp_exec.indirect_non_call" }, \
616 { 0x89, 0x30, C0|C1|C2|C3, "br_misp_exec.near_calls" }, \
618 { 0x89, 0x07, C0|C1|C2|C3, "br_misp_exec.non_calls" }, \
619 { 0x89, 0x08, C0|C1|C2|C3, "br_misp_exec.return_near" }, \
620 { 0x89, 0x40, C0|C1|C2|C3, "br_misp_exec.taken" }, \
622 { 0x17, 0x01, C0|C1|C2|C3, "inst_queue_writes" }, \
623 { 0x1E, 0x01, C0|C1|C2|C3, "inst_queue_write_cycles" }, \
624 { 0xA7, 0x01, C0|C1|C2|C3, "baclear_force_iq" }, \
626 { 0xD0, 0x01, C0|C1|C2|C3, "macro_insts.decoded" }, \
627 { 0xA6, 0x01, C0|C1|C2|C3, "macro_insts.fusions_decoded" }, \
628 { 0x19, 0x01, C0|C1|C2|C3, "two_uop_insts_decoded" }, \
630 { 0x18, 0x01, C0|C1|C2|C3, "inst_decoded.dec0" }, \
631 { 0xD1, 0x04, C0|C1|C2|C3, "uops_decoded.esp_folding" }, \
632 { 0xD1, 0x08, C0|C1|C2|C3, "uops_decoded.esp_sync" }, \
634 { 0xD1, 0x02, C0|C1|C2|C3, "uops_decoded.ms" }, \
635 { 0x20, 0x01, C0|C1|C2|C3, "lsd_overflow" }, \
636 { 0x0E, 0x01, C0|C1|C2|C3, "uops_issued.any" }, \
638 { 0x0E, 0x02, C0|C1|C2|C3, "uops_issued.fused" }, \
639 { 0xA2, 0x20, C0|C1|C2|C3, "resource_stalls.fpcw" }, \
640 { 0xA2, 0x02, C0|C1|C2|C3, "resource_stalls.load" }, \
642 { 0xA2, 0x40, C0|C1|C2|C3, "resource_stalls.mxcsr" }, \
643 { 0xA2, 0x04, C0|C1|C2|C3, "resource_stalls.rs_full" }, \
644 { 0xA2, 0x08, C0|C1|C2|C3, "resource_stalls.store" }, \
646 { 0xA2, 0x01, C0|C1|C2|C3, "resource_stalls.any" }, \
647 { 0xD2, 0x01, C0|C1|C2|C3, "rat_stalls.flags" }, \
648 { 0xD2, 0x02, C0|C1|C2|C3, "rat_stalls.registers" }, \
650 { 0xD2, 0x04, C0|C1|C2|C3, "rat_stalls.rob_read_port" }, \
651 { 0xD2, 0x08, C0|C1|C2|C3, "rat_stalls.scoreboard" }, \
652 { 0xD2, 0x0F, C0|C1|C2|C3, "rat_stalls.any" }, \
654 { 0xD4, 0x01, C0|C1|C2|C3, "seg_rename_stalls" }, \
655 { 0xD5, 0x01, C0|C1|C2|C3, "es_reg_renames" }, \
656 { 0x10, 0x02, C0|C1|C2|C3, "fp_comp_ops_exe.mmx" }, \
658 { 0x10, 0x80, C0|C1|C2|C3, "fp_comp_ops_exe.sse_double_precision" }, \
659 { 0x10, 0x04, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp" }, \
660 { 0x10, 0x10, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp_packed" }, \
662 { 0x10, 0x20, C0|C1|C2|C3, "fp_comp_ops_exe.sse_fp_scalar" }, \
663 { 0x10, 0x40, C0|C1|C2|C3, "fp_comp_ops_exe.sse_single_precision" }, \
664 { 0x10, 0x08, C0|C1|C2|C3, "fp_comp_ops_exe.sse2_integer" }, \
666 { 0x10, 0x01, C0|C1|C2|C3, "fp_comp_ops_exe.x87" }, \
667 { 0x14, 0x01, C0|C1|C2|C3, "arith.cycles_div_busy" }, \
668 { 0x14, 0x02, C0|C1|C2|C3, "arith.mul" }, \
670 { 0x12, 0x04, C0|C1|C2|C3, "simd_int_128.pack" }, \
671 { 0x12, 0x20, C0|C1|C2|C3, "simd_int_128.packed_arith" }, \
672 { 0x12, 0x10, C0|C1|C2|C3, "simd_int_128.packed_logical" }, \
674 { 0x12, 0x01, C0|C1|C2|C3, "simd_int_128.packed_mpy" }, \
675 { 0x12, 0x02, C0|C1|C2|C3, "simd_int_128.packed_shift" }, \
676 { 0x12, 0x40, C0|C1|C2|C3, "simd_int_128.shuffle_move" }, \
678 { 0x12, 0x08, C0|C1|C2|C3, "simd_int_128.unpack" }, \
679 { 0xFD, 0x04, C0|C1|C2|C3, "simd_int_64.pack" }, \
680 { 0xFD, 0x20, C0|C1|C2|C3, "simd_int_64.packed_arith" }, \
682 { 0xFD, 0x10, C0|C1|C2|C3, "simd_int_64.packed_logical" }, \
683 { 0xFD, 0x01, C0|C1|C2|C3, "simd_int_64.packed_mpy" }, \
684 { 0xFD, 0x02, C0|C1|C2|C3, "simd_int_64.packed_shift" }, \
686 { 0xFD, 0x40, C0|C1|C2|C3, "simd_int_64.shuffle_move" }, \
687 { 0xFD, 0x08, C0|C1|C2|C3, "simd_int_64.unpack" }, \
688 { 0xB1, 0x01, C0|C1|C2|C3, "uops_executed.port0" }, \
690 { 0xB1, 0x02, C0|C1|C2|C3, "uops_executed.port1" }, \
691 { 0x40, 0x04, C0|C1, "l1d_cache_ld.e_state" }, \
692 { 0x40, 0x01, C0|C1, "l1d_cache_ld.i_state" }, \
694 { 0x40, 0x08, C0|C1, "l1d_cache_ld.m_state" }, \
695 { 0x40, 0x0F, C0|C1, "l1d_cache_ld.mesi" }, \
696 { 0x40, 0x02, C0|C1, "l1d_cache_ld.s_state" }, \
698 { 0x41, 0x04, C0|C1, "l1d_cache_st.e_state" }, \
699 { 0x41, 0x08, C0|C1, "l1d_cache_st.m_state" }, \
700 { 0x41, 0x0F, C0|C1, "l1d_cache_st.mesi" }, \
702 { 0x41, 0x02, C0|C1, "l1d_cache_st.s_state" }, \
703 { 0x42, 0x04, C0|C1, "l1d_cache_lock.e_state" }, \
704 { 0x42, 0x01, C0|C1, "l1d_cache_lock.hit" }, \
706 { 0x42, 0x08, C0|C1, "l1d_cache_lock.m_state" }, \
707 { 0x42, 0x02, C0|C1, "l1d_cache_lock.s_state" }, \
708 { 0x43, 0x01, C0|C1, "l1d_all_ref.any" }, \
710 { 0x43, 0x02, C0|C1, "l1d_all_ref.cacheable" }, \
711 { 0x4B, 0x01, C0|C1, "mmx2_mem_exec.nta" }, \
712 { 0x4C, 0x01, C0|C1, "load_hit_pre" }, \
714 { 0x4E, 0x02, C0|C1, "l1d_prefetch.miss" }, \
715 { 0x4E, 0x01, C0|C1, "l1d_prefetch.requests" }, \
716 { 0x4E, 0x04, C0|C1, "l1d_prefetch.triggers" }, \
718 { 0x51, 0x04, C0|C1, "l1d.m_evict" }, \
719 { 0x51, 0x02, C0|C1, "l1d.m_repl" }, \
720 { 0x51, 0x08, C0|C1, "l1d.m_snoop_evict" }, \
722 { 0x51, 0x01, C0|C1, "l1d.repl" }, \
723 { 0x52, 0x01, C0|C1, "l1d_cache_prefetch_lock_fb_hit" }, \
724 { 0x53, 0x01, C0|C1, "l1d_cache_lock_fb_hit" }, \
726 { 0x63, 0x02, C0|C1, "cache_lock_cycles.l1d" }, \
727 { 0x63, 0x01, C0|C1, "cache_lock_cycles.l1d_l2" }, \
728 { 0x06, 0x04, C0|C1|C2|C3, "store_blocks.at_ret" }, \
730 { 0x06, 0x08, C0|C1|C2|C3, "store_blocks.l1d_block" }, \
731 { 0x06, 0x01, C0|C1|C2|C3, "store_blocks.not_sta" }, \
732 { 0x06, 0x02, C0|C1|C2|C3, "store_blocks.sta" }, \
734 { 0x13, 0x07, C0|C1|C2|C3, "load_dispatch.any" }, \
735 { 0x13, 0x04, C0|C1|C2|C3, "load_dispatch.mob" }, \
736 { 0x13, 0x01, C0|C1|C2|C3, "load_dispatch.rs" }, \
738 { 0x13, 0x02, C0|C1|C2|C3, "load_dispatch.rs_delayed" }, \
739 { 0x08, 0x01, C0|C1|C2|C3, "dtlb_load_misses.any" }, \
740 { 0x08, 0x20, C0|C1|C2|C3, "dtlb_load_misses.pde_miss" }, \
742 { 0x08, 0x02, C0|C1|C2|C3, "dtlb_load_misses.walk_completed" }, \
743 { 0x49, 0x01, C0|C1|C2|C3, "dtlb_misses.any" }, \
744 { 0x49, 0x10, C0|C1|C2|C3, "dtlb_misses.stlb_hit" }, \
746 { 0x49, 0x02, C0|C1|C2|C3, "dtlb_misses.walk_completed" }, \
747 { 0x4F, 0x02, C0|C1|C2|C3, "ept.epde_miss" }, \
748 { 0x4F, 0x08, C0|C1|C2|C3, "ept.epdpe_miss" }, \
750 { 0x85, 0x01, C0|C1|C2|C3, "itlb_misses.any" }, \
751 { 0x85, 0x02, C0|C1|C2|C3, "itlb_misses.walk_completed" }, \
752 { 0x24, 0xAA, C0|C1|C2|C3, "l2_rqsts.miss" }, \
754 { 0x24, 0xFF, C0|C1|C2|C3, "l2_rqsts.references" }, \
755 { 0x24, 0x10, C0|C1|C2|C3, "l2_rqsts.ifetch_hit" }, \
756 { 0x24, 0x20, C0|C1|C2|C3, "l2_rqsts.ifetch_miss" }, \
758 { 0x24, 0x30, C0|C1|C2|C3, "l2_rqsts.ifetches" }, \
759 { 0x24, 0x01, C0|C1|C2|C3, "l2_rqsts.ld_hit" }, \
760 { 0x24, 0x02, C0|C1|C2|C3, "l2_rqsts.ld_miss" }, \
762 { 0x24, 0x03, C0|C1|C2|C3, "l2_rqsts.loads" }, \
763 { 0x24, 0x40, C0|C1|C2|C3, "l2_rqsts.prefetch_hit" }, \
764 { 0x24, 0x80, C0|C1|C2|C3, "l2_rqsts.prefetch_miss" }, \
766 { 0x24, 0xC0, C0|C1|C2|C3, "l2_rqsts.prefetches" }, \
767 { 0x24, 0x04, C0|C1|C2|C3, "l2_rqsts.rfo_hit" }, \
768 { 0x24, 0x08, C0|C1|C2|C3, "l2_rqsts.rfo_miss" }, \
770 { 0x24, 0x0C, C0|C1|C2|C3, "l2_rqsts.rfos" }, \
771 { 0x26, 0xFF, C0|C1|C2|C3, "l2_data_rqsts.any" }, \
772 { 0x26, 0x04, C0|C1|C2|C3, "l2_data_rqsts.demand.e_state" }, \
774 { 0x26, 0x01, C0|C1|C2|C3, "l2_data_rqsts.demand.i_state" }, \
775 { 0x26, 0x08, C0|C1|C2|C3, "l2_data_rqsts.demand.m_state" }, \
776 { 0x26, 0x0F, C0|C1|C2|C3, "l2_data_rqsts.demand.mesi" }, \
778 { 0x26, 0x02, C0|C1|C2|C3, "l2_data_rqsts.demand.s_state" }, \
779 { 0x26, 0x40, C0|C1|C2|C3, "l2_data_rqsts.prefetch.e_state" }, \
780 { 0x26, 0x10, C0|C1|C2|C3, "l2_data_rqsts.prefetch.i_state" }, \
782 { 0x26, 0x80, C0|C1|C2|C3, "l2_data_rqsts.prefetch.m_state" }, \
783 { 0x26, 0xF0, C0|C1|C2|C3, "l2_data_rqsts.prefetch.mesi" }, \
784 { 0x26, 0x20, C0|C1|C2|C3, "l2_data_rqsts.prefetch.s_state" }, \
786 { 0x27, 0x40, C0|C1|C2|C3, "l2_write.lock.e_state" }, \
787 { 0x27, 0x10, C0|C1|C2|C3, "l2_write.lock.i_state" }, \
788 { 0x27, 0x20, C0|C1|C2|C3, "l2_write.lock.s_state" }, \
790 { 0x27, 0x0E, C0|C1|C2|C3, "l2_write.rfo.hit" }, \
791 { 0x27, 0x01, C0|C1|C2|C3, "l2_write.rfo.i_state" }, \
792 { 0x27, 0x08, C0|C1|C2|C3, "l2_write.rfo.m_state" }, \
794 { 0x27, 0x0F, C0|C1|C2|C3, "l2_write.rfo.mesi" }, \
795 { 0x27, 0x02, C0|C1|C2|C3, "l2_write.rfo.s_state" }, \
796 { 0x28, 0x04, C0|C1|C2|C3, "l1d_wb_l2.e_state" }, \
798 { 0x28, 0x01, C0|C1|C2|C3, "l1d_wb_l2.i_state" }, \
799 { 0x28, 0x08, C0|C1|C2|C3, "l1d_wb_l2.m_state" }, \
800 { 0xF0, 0x80, C0|C1|C2|C3, "l2_transactions.any" }, \
802 { 0xF0, 0x20, C0|C1|C2|C3, "l2_transactions.fill" }, \
803 { 0xF0, 0x04, C0|C1|C2|C3, "l2_transactions.ifetch" }, \
804 { 0xF0, 0x10, C0|C1|C2|C3, "l2_transactions.l1d_wb" }, \
806 { 0xF0, 0x01, C0|C1|C2|C3, "l2_transactions.load" }, \
807 { 0xF0, 0x08, C0|C1|C2|C3, "l2_transactions.prefetch" }, \
808 { 0xF0, 0x02, C0|C1|C2|C3, "l2_transactions.rfo" }, \
810 { 0xF0, 0x40, C0|C1|C2|C3, "l2_transactions.wb" }, \
811 { 0xF1, 0x07, C0|C1|C2|C3, "l2_lines_in.any" }, \
812 { 0xF1, 0x04, C0|C1|C2|C3, "l2_lines_in.e_state" }, \
814 { 0xF1, 0x02, C0|C1|C2|C3, "l2_lines_in.s_state" }, \
815 { 0xF2, 0x0F, C0|C1|C2|C3, "l2_lines_out.any" }, \
816 { 0xF2, 0x01, C0|C1|C2|C3, "l2_lines_out.demand_clean" }, \
818 { 0xF2, 0x02, C0|C1|C2|C3, "l2_lines_out.demand_dirty" }, \
819 { 0xF2, 0x04, C0|C1|C2|C3, "l2_lines_out.prefetch_clean" }, \
820 { 0x6C, 0x01, C0|C1|C2|C3, "io_transactions" }, \
822 { 0xB0, 0x80, C0|C1|C2|C3, "offcore_requests.any" }, \
823 { 0xB0, 0x10, C0|C1|C2|C3, "offcore_requests.any.rfo" }, \
824 { 0xB0, 0x40, C0|C1|C2|C3, "offcore_requests.l1d_writeback" }, \
826 { 0xB8, 0x01, C0|C1|C2|C3, "snoop_response.hit" }, \
827 { 0xB8, 0x02, C0|C1|C2|C3, "snoop_response.hite" }, \
828 { 0xB8, 0x04, C0|C1|C2|C3, "snoop_response.hitm" }, \
830 { 0xF4, 0x10, C0|C1|C2|C3, "sq_misc.split_lock" }, \
831 { 0x0B, 0x01, C0|C1|C2|C3, "mem_inst_retired.loads" }, \
832 { 0x0B, 0x02, C0|C1|C2|C3, "mem_inst_retired.stores" }, \
834 { 0xC0, 0x04, C0|C1|C2|C3, "inst_retired.mmx" }, \
835 { 0xC0, 0x02, C0|C1|C2|C3, "inst_retired.x87" }, \
836 { 0xC7, 0x04, C0|C1|C2|C3, "ssex_uops_retired.packed_double" }, \
838 { 0xC7, 0x01, C0|C1|C2|C3, "ssex_uops_retired.packed_single" }, \
839 { 0xC7, 0x08, C0|C1|C2|C3, "ssex_uops_retired.scalar_double" }, \
840 { 0xC7, 0x02, C0|C1|C2|C3, "ssex_uops_retired.scalar_single" }, \
842 { 0xC7, 0x10, C0|C1|C2|C3, "ssex_uops_retired.vector_integer" }, \
843 { 0xC2, 0x01, C0|C1|C2|C3, "uops_retired.any" }, \
844 { 0xC2, 0x04, C0|C1|C2|C3, "uops_retired.macro_fused" }, \
846 { 0xC8, 0x20, C0|C1|C2|C3, "itlb_miss_retired" }, \
847 { 0xCB, 0x80, C0|C1|C2|C3, "mem_load_retired.dtlb_miss" }, \
848 { 0xCB, 0x40, C0|C1|C2|C3, "mem_load_retired.hit_lfb" }, \
850 { 0xCB, 0x01, C0|C1|C2|C3, "mem_load_retired.l1d_hit" }, \
851 { 0xCB, 0x02, C0|C1|C2|C3, "mem_load_retired.l2_hit" }, \
852 { 0xCB, 0x10, C0|C1|C2|C3, "mem_load_retired.llc_miss" }, \
854 { 0xCB, 0x04, C0|C1|C2|C3, "mem_load_retired.llc_unshared_hit" }, \
855 { 0xCB, 0x08, C0|C1|C2|C3, "mem_load_retired.other_core_l2_hit_hitm" }, \
856 { 0x0F, 0x02, C0|C1|C2|C3, "mem_uncore_retired.other_core_l2_hitm" }, \
858 { 0x0F, 0x08, C0|C1|C2|C3, "mem_uncore_retired.remote_cache_local_home_hit" },\
859 { 0x0F, 0x10, C0|C1|C2|C3, "mem_uncore_retired.remote_dram" }, \
860 { 0x0F, 0x20, C0|C1|C2|C3, "mem_uncore_retired.local_dram" }, \
862 { 0x0C, 0x01, C0|C1|C2|C3, "mem_store_retired.dtlb_miss" }, \
863 { 0xC4, 0x01, C0|C1|C2|C3, "br_inst_retired.conditional" }, \
864 { 0xC4, 0x02, C0|C1|C2|C3, "br_inst_retired.near_call" }, \
866 { 0xC5, 0x02, C0|C1|C2|C3, "br_misp_retired.near_call" }, \
867 { 0xDB, 0x01, C0|C1|C2|C3, "uop_unfusion" }, \
868 { 0xF7, 0x01, C0|C1|C2|C3, "fp_assist.all" }, \
870 { 0xF7, 0x04, C0|C1|C2|C3, "fp_assist.input" }, \
871 { 0xF7, 0x02, C0|C1|C2|C3, "fp_assist.output" }, \
872 { 0xCC, 0x03, C0|C1|C2|C3, "fp_mmx_trans.any" }, \
874 { 0xCC, 0x01, C0|C1|C2|C3, "fp_mmx_trans.to_fp" }, \
875 { 0xCC, 0x02, C0|C1|C2|C3, "fp_mmx_trans.to_mmx" }, \
876 { 0xC3, 0x04, C0|C1|C2|C3, "machine_clears.smc" }
879 { 0xc4, 0x00, C0|C1, "PAPI_br_ins" }, /* br_inst_retired.any */ \
880 { 0xc5, 0x00, C0|C1, "PAPI_br_msp" }, /* br_inst_retired.mispred */ \
881 { 0xc4, 0x03, C0|C1, "PAPI_br_ntk" }, \
883 { 0xc4, 0x05, C0|C1, "PAPI_br_prc" }, \
885 { 0xc8, 0x00, C0|C1, "PAPI_hw_int" }, /* hw_int_rcv */ \
886 { 0xaa, 0x03, C0|C1, "PAPI_tot_iis" }, /* macro_insts.all_decoded */ \
887 { 0x40, 0x23, C0|C1, "PAPI_l1_dca" }, /* l1d_cache.l1|st */ \
888 { 0x2a, 0x41, C0|C1, "PAPI_l2_stm" }, /* l2_st.self.i_state */ \
889 { 0x2e, 0x4f, C0|C1, "PAPI_l2_tca" }, /* longest_lat_cache.reference */ \
890 { 0x2e, 0x4e, C0|C1, "PAPI_l2_tch" }, /* l2_rqsts.mes */ \
891 { 0x2e, 0x41, C0|C1, "PAPI_l2_tcm" }, /* longest_lat_cache.miss */ \
892 { 0x2a, 0x4f, C0|C1, "PAPI_l2_tcw" }, /* l2_st.self.mesi */ \
893 { 0x08, 0x07, C0|C1, "PAPI_tlb_dm" }, /* data_tlb_misses.dtlb.miss */ \
894 { 0x82, 0x02, C0|C1, "PAPI_tlb_im" } /* itlb.misses */
898 { 0x2, 0x81, C0|C1, "store_forwards.good" }, \
899 { 0x6, 0x0, C0|C1, "segment_reg_loads.any" }, \
900 { 0x7, 0x1, C0|C1, "prefetch.prefetcht0" }, \
901 { 0x7, 0x6, C0|C1, "prefetch.sw_l2" }, \
902 { 0x7, 0x8, C0|C1, "prefetch.prefetchnta" }, \
903 { 0x8, 0x7, C0|C1, "data_tlb_misses.dtlb_miss" }, \
904 { 0x8, 0x5, C0|C1, "data_tlb_misses.dtlb_miss_ld" }, \
905 { 0x8, 0x9, C0|C1, "data_tlb_misses.l0_dtlb_miss_ld" }, \
906 { 0x8, 0x6, C0|C1, "data_tlb_misses.dtlb_miss_st" }, \
907 { 0xC, 0x3, C0|C1, "page_walks.cycles" }, \
908 { 0x10, 0x1, C0|C1, "x87_comp_ops_exe.any.s" }, \
909 { 0x10, 0x81, C0|C1, "x87_comp_ops_exe.any.ar" }, \
910 { 0x11, 0x1, C0|C1, "fp_assist" }, \
911 { 0x11, 0x81, C0|C1, "fp_assist.ar" }, \
912 { 0x12, 0x1, C0|C1, "mul.s" }, \
913 { 0x12, 0x81, C0|C1, "mul.ar" }, \
914 { 0x13, 0x1, C0|C1, "div.s" }, \
915 { 0x13, 0x81, C0|C1, "div.ar" }, \
916 { 0x14, 0x1, C0|C1, "cycles_div_busy" }, \
917 { 0x21, 0x0, C0|C1, "l2_ads" }, \
918 { 0x22, 0x0, C0|C1, "l2_dbus_busy" }, \
919 { 0x24, 0x0, C0|C1, "l2_lines_in" }, \
920 { 0x25, 0x0, C0|C1, "l2_m_lines_in" }, \
921 { 0x26, 0x0, C0|C1, "l2_lines_out" }, \
922 { 0x27, 0x0, C0|C1, "l2_m_lines_out" }, \
923 { 0x28, 0x0, C0|C1, "l2_ifetch" }, \
924 { 0x29, 0x0, C0|C1, "l2_ld" }, \
925 { 0x2A, 0x0, C0|C1, "l2_st" }, \
926 { 0x2B, 0x0, C0|C1, "l2_lock" }, \
927 { 0x2E, 0x0, C0|C1, "l2_rqsts" }, \
928 { 0x2E, 0x41, C0|C1, "l2_rqsts.self.demand.i_state" }, \
929 { 0x2E, 0x4F, C0|C1, "l2_rqsts.self.demand.mesi" }, \
930 { 0x30, 0x0, C0|C1, "l2_reject_bus_q" }, \
931 { 0x32, 0x0, C0|C1, "l2_no_req" }, \
932 { 0x3A, 0x0, C0|C1, "eist_trans" }, \
933 { 0x3B, 0xC0, C0|C1, "thermal_trip" }, \
934 { 0x3C, 0x0, C0|C1, "cpu_clk_unhalted.core_p" }, \
935 { 0x3C, 0x1, C0|C1, "cpu_clk_unhalted.bus" }, \
936 { 0x3C, 0x2, C0|C1, "cpu_clk_unhalted.no_other" }, \
937 { 0x40, 0x21, C0|C1, "l1d_cache.ld" }, \
938 { 0x40, 0x22, C0|C1, "l1d_cache.st" }, \
939 { 0x60, 0x0, C0|C1, "bus_request_outstanding" }, \
940 { 0x61, 0x0, C0|C1, "bus_bnr_drv" }, \
941 { 0x62, 0x0, C0|C1, "bus_drdy_clocks" }, \
942 { 0x63, 0x0, C0|C1, "bus_lock_clocks" }, \
943 { 0x64, 0x0, C0|C1, "bus_data_rcv" }, \
944 { 0x65, 0x0, C0|C1, "bus_trans_brd" }, \
945 { 0x66, 0x0, C0|C1, "bus_trans_rfo" }, \
946 { 0x67, 0x0, C0|C1, "bus_trans_wb" }, \
947 { 0x68, 0x0, C0|C1, "bus_trans_ifetch" }, \
948 { 0x69, 0x0, C0|C1, "bus_trans_inval" }, \
949 { 0x6A, 0x0, C0|C1, "bus_trans_pwr" }, \
950 { 0x6B, 0x0, C0|C1, "bus_trans_p" }, \
951 { 0x6C, 0x0, C0|C1, "bus_trans_io" }, \
952 { 0x6D, 0x0, C0|C1, "bus_trans_def" }, \
953 { 0x6E, 0x0, C0|C1, "bus_trans_burst" }, \
954 { 0x6F, 0x0, C0|C1, "bus_trans_mem" }, \
955 { 0x70, 0x0, C0|C1, "bus_trans_any" }, \
956 { 0x77, 0x0, C0|C1, "ext_snoop" }, \
957 { 0x7A, 0x0, C0|C1, "bus_hit_drv" }, \
958 { 0x7B, 0x0, C0|C1, "bus_hitm_drv" }, \
959 { 0x7D, 0x0, C0|C1, "busq_empty" }, \
960 { 0x7E, 0x0, C0|C1, "snoop_stall_drv" }, \
961 { 0x7F, 0x0, C0|C1, "bus_io_wait" }, \
962 { 0x80, 0x3, C0|C1, "icache.accesses" }, \
963 { 0x80, 0x2, C0|C1, "icache.misses" }, \
964 { 0x82, 0x4, C0|C1, "itlb.flush" }, \
965 { 0x82, 0x2, C0|C1, "itlb.misses" }, \
966 { 0xAA, 0x2, C0|C1, "macro_insts.cisc_decoded" }, \
967 { 0xAA, 0x3, C0|C1, "macro_insts.all_decoded" }, \
968 { 0xB0, 0x0, C0|C1, "simd_uops_exec.s" }, \
969 { 0xB0, 0x80, C0|C1, "simd_uops_exec.ar" }, \
970 { 0xB1, 0x0, C0|C1, "simd_sat_uop_exec.s" }, \
971 { 0xB1, 0x80, C0|C1, "simd_sat_uop_exec.ar" }, \
972 { 0xB3, 0x1, C0|C1, "simd_uop_type_exec.mul.s" }, \
973 { 0xB3, 0x81, C0|C1, "simd_uop_type_exec.mul.ar" }, \
974 { 0xB3, 0x02, C0|C1, "simd_uop_type_exec.shift.s" }, \
975 { 0xB3, 0x82, C0|C1, "simd_uop_type_exec.shift.ar" }, \
976 { 0xB3, 0x04, C0|C1, "simd_uop_type_exec.pack.s" }, \
977 { 0xB3, 0x84, C0|C1, "simd_uop_type_exec.pack.ar" }, \
978 { 0xB3, 0x08, C0|C1, "simd_uop_type_exec.unpack.s" }, \
979 { 0xB3, 0x88, C0|C1, "simd_uop_type_exec.unpack.ar" }, \
980 { 0xB3, 0x10, C0|C1, "simd_uop_type_exec.logical.s" }, \
981 { 0xB3, 0x90, C0|C1, "simd_uop_type_exec.logical.ar" }, \
982 { 0xB3, 0x20, C0|C1, "simd_uop_type_exec.arithmetic.s" }, \
983 { 0xB3, 0xA0, C0|C1, "simd_uop_type_exec.arithmetic.ar" }, \
984 { 0xC2, 0x10, C0|C1, "uops_retired.any" }, \
985 { 0xC3, 0x1, C0|C1, "machine_clears.smc" }, \
986 { 0xC4, 0x0, C0|C1, "br_inst_retired.any" }, \
987 { 0xC4, 0x1, C0|C1, "br_inst_retired.pred_not_taken" }, \
988 { 0xC4, 0x2, C0|C1, "br_inst_retired.mispred_not_taken" }, \
989 { 0xC4, 0x4, C0|C1, "br_inst_retired.pred_taken" }, \
990 { 0xC4, 0x8, C0|C1, "br_inst_retired.mispred_taken" }, \
991 { 0xC4, 0xA, C0|C1, "br_inst_retired.mispred" }, \
992 { 0xC4, 0xC, C0|C1, "br_inst_retired.taken" }, \
993 { 0xC4, 0xF, C0|C1, "br_inst_retired.any1" }, \
994 { 0xC6, 0x1, C0|C1, "cycles_int_masked.cycles_int_masked" }, \
995 { 0xC6, 0x2, C0|C1, \
997 { 0xC7, 0x1, C0|C1, "simd_inst_retired.packed_single" }, \
998 { 0xC7, 0x2, C0|C1, "simd_inst_retired.scalar_single" }, \
999 { 0xC7, 0x4, C0|C1, "simd_inst_retired.packed_double" }, \
1000 { 0xC7, 0x8, C0|C1, "simd_inst_retired.scalar_double" }, \
1001 { 0xC7, 0x10, C0|C1, "simd_inst_retired.vector" }, \
1002 { 0xC7, 0x1F, C0|C1, "simd_inst_retired.any" }, \
1003 { 0xC8, 0x00, C0|C1, "hw_int_rcv" }, \
1004 { 0xCA, 0x1, C0|C1, "simd_comp_inst_retired.packed_single" }, \
1005 { 0xCA, 0x2, C0|C1, "simd_comp_inst_retired.scalar_single" }, \
1006 { 0xCA, 0x4, C0|C1, "simd_comp_inst_retired.packed_double" }, \
1007 { 0xCA, 0x8, C0|C1, "simd_comp_inst_retired.scalar_double" }, \
1008 { 0xCB, 0x1, C0|C1, "mem_load_retired.l2_hit" }, \
1009 { 0xCB, 0x2, C0|C1, "mem_load_retired.l2_miss" }, \
1010 { 0xCB, 0x4, C0|C1, "mem_load_retired.dtlb_miss" }, \
1011 { 0xCD, 0x0, C0|C1, "simd_assist" }, \
1012 { 0xCE, 0x0, C0|C1, "simd_instr_retired" }, \
1013 { 0xCF, 0x0, C0|C1, "simd_sat_instr_retired" }, \
1014 { 0xE0, 0x1, C0|C1, "br_inst_decoded" }, \
1015 { 0xE4, 0x1, C0|C1, "bogus_br" }, \
1016 { 0xE6, 0x1, C0|C1, "baclears.any" }