Lines Matching defs:dip
46 pcieb_peekpoke_cb(dev_info_t *dip, ddi_fm_error_t *derr) {
47 pf_eh_enter(PCIE_DIP2BUS(dip));
48 (void) pf_scan_fabric(dip, derr, NULL);
49 pf_eh_exit(PCIE_DIP2BUS(dip));
53 pcieb_set_prot_scan(dev_info_t *dip, ddi_acc_impl_t *hdlp)
56 ddi_get_instance(dip));
60 hdlp->ahi_scan_dip = dip;
65 pcieb_plat_peekpoke(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop,
69 ddi_get_instance(dip));
71 if (!PCIE_IS_RP(PCIE_DIP2BUS(dip)))
72 return (ddi_ctlops(dip, rdip, ctlop, arg, result));
74 return (pci_peekpoke_check(dip, rdip, ctlop, arg, result,
82 pcieb_plat_attach_workaround(dev_info_t *dip)
85 pcieb_intel_error_workaround(dip);
86 pcieb_intel_mps_workaround(dip);
92 pcieb_intel_error_workaround(dev_info_t *dip)
95 ddi_get_instance(dip));
97 pcieb_intel_serr_workaround(dip, pcieb->pcieb_no_aer_msi);
98 pcieb_intel_rber_workaround(dip);
99 pcieb_intel_sw_workaround(dip);
103 pcieb_plat_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
106 return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result));
112 pcieb_plat_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle)
123 pcishpc_init(dev_info_t *dip)
130 pcishpc_uninit(dev_info_t *dip)
137 pcishpc_intr(dev_info_t *dip)
144 pcieb_plat_pwr_disable(dev_info_t *dip)
151 pcieb_plat_msi_supported(dev_info_t *dip)
153 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
458 pcieb_intel_serr_workaround(dev_info_t *dip, boolean_t mcheck)
465 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
476 PCIEB_DEBUG(DBG_ATTACH, dip, "VID:0x%x DID:0x%x RID:0x%x bdf=0x%x\n",
489 pcie_set_rber_fatal(dip, B_TRUE);
530 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf:%x mcheck:%d size:%d "
549 pcieb_intel_rber_workaround(dev_info_t *dip)
552 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
561 if (!pcie_get_rber_fatal(dip))
580 pcieb_intel_mps_workaround(dev_info_t *dip)
584 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
608 pcieb_intel_sw_workaround(dev_info_t *dip)
611 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
617 if (!PCIE_IS_SW(PCIE_DIP2BUS(dip)))