89 	uint8_t			dev;
98 	uchar_t dev;
133 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id);
136 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
818 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id)
829 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
833 	cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
837 		curcap = pci_getb(bus, dev, func, cap_id_loc);
843 		cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1);
894 	uchar_t bus, dev, func;
927 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
933 	cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E);
935 		cmd_reg = pci_getw(bus, dev, func,
940 			    bus, dev, func);
945 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
948 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
975 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
979 			    "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
1053 				    bus, dev, func, (uint32_t)addr,
1070 				    bus, dev, func, (uint32_t)addr,
1083 	io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
1084 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
1148 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
1150 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
1152 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
1153 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
1158 			    bus, dev, func, io_base, io_limit);
1166 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
1168 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
1230 			pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
1232 			pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
1247 				pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW,
1249 				pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW,
1251 				pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH,
1253 				pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH,
1261 			    bus, dev, func, mem_base, mem_limit);
1271 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
1410 	/* All dev programmed, so we can create available prop */
1509 	uchar_t dev, func, nfunc, header;
1530 				    entry->dev, entry->func, CONFIG_NEW, 0);
1538 	for (dev = 0; dev < max_dev_pci; dev++) {
1542 			dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x",
1543 			    dev, func);
1545 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1552 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1575 				process_devfunc(bus, dev, func, header,
1717 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1729 	newundo->dev = dev;
1760 	uint8_t bus, dev, fn;
1769 		dev = undolist->dev;
1772 		(*(undolist->undofn))(bus, dev, fn);
1781 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1785 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1791 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1795 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1799 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1811 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1813 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1817 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1825 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1829 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1831 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR);
1833 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1839 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1841 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1844 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1847 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1856 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
1874 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
1878 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
1879 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
1882 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
1883 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
1896 			pci_fix_amd8111(bus, dev, func);
1902 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
1930 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid,
1934 	bdf = PCI_GETBDF(bus, dev, func);
1945 			secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
1946 			subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
1969 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
1972 		    "%x,%x", dev, func);
1983 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
1984 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
2001 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
2009 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
2033 	set_devpm_d0(bus, dev, func);
2036 		add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge);
2046 		entry->dev = dev;
2053 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
2057 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
2059 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
2096 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
2350 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2376 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
2381 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
2382 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
2383 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2384 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
2423 		base = pci_getl(bus, dev, func, offset);
2425 			command = (uint_t)pci_getw(bus, dev, func,
2427 			pci_putw(bus, dev, func, PCI_CONF_COMM,
2430 		pci_putl(bus, dev, func, offset, 0xffffffff);
2431 		value = pci_getl(bus, dev, func, offset);
2432 		pci_putl(bus, dev, func, offset, base);
2434 			pci_putw(bus, dev, func, PCI_CONF_COMM, command);
2507 					pci_putl(bus, dev, func, offset,
2509 					base = pci_getl(bus, dev, func, offset);
2516 					    bus, dev, func, offset, len);
2526 				base_hi = pci_getl(bus, dev, func, offset + 4);
2632 					pci_putl(bus, dev, func, offset,
2634 					base = pci_getl(bus, dev, func, offset);
2640 					    bus, dev, func, offset, len);
2662 	base = pci_getl(bus, dev, func, offset);
2663 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2664 	value = pci_getl(bus, dev, func, offset);
2665 	pci_putl(bus, dev, func, offset, base);
2768 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2774 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2775 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2783 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2853 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
2855 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
2857 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
2862 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
2864 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
2866 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
2867 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
2886 		    pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) {
2888 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2893 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
2895 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
2916 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
2918 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
2938 		    pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) {
2940 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2953 	if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) &
3263 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
3273 	lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
3280 		hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
3335 	/* set mask to 1 as there is only one slot (i.e dev 0) */

Indexes created Tue Jul 24 14:28:13 CEST 2018