Lines Matching defs:rev
210 uint32_t rev = mc->mc_props.mcp_rev;
215 return (MC_REV_MATCH(rev, MC_F_REVS_BCDE) ?
223 uint32_t rev = mc->mc_props.mcp_rev;
228 return (MC_REV_MATCH(rev, MC_F_REVS_BCDE) ?
536 uint32_t rev = mcp->mcp_rev;
562 * in AM2 and S1g1 packages only, but in all rev F/G cases we
565 if (MC_REV_MATCH(rev, MC_F_REVS_FG))
578 if (mcdcfg_lookup(rev, mcp->mcp_mod64mux, mcp->mcp_accwidth,
729 uint32_t rev = mc->mc_props.mcp_rev;
736 if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
789 uint32_t rev = mc->mc_props.mcp_rev;
811 if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
821 * these revs - for rev E it is in DRAM config low.
823 if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
827 } else if (MC_REV_MATCH(rev, MC_F_REV_E)) {
835 * is enabled - in rev F that has moved to dram config hi register.
842 * introduced as an option in rev E, but the bit that indicates it
845 if (MC_REV_MATCH(rev, MC_F_REV_E)) {
848 } else if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
858 maskdivisor = MC_REV_MATCH(rev, MC_F_REVS_FG) ? 2 : 1;
876 if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
912 csbase = MC_CSBASE(&base[i], rev);
913 csmask = MC_CSMASK(&mask[i / maskdivisor], rev);
939 for (bitno = MC_CSMASKLO_LOBIT(rev);
940 bitno <= MC_CSMASKLO_HIBIT(rev); bitno++) {
1060 return (ENOTSUP); /* MC rev does not offer online spare */
1404 uint32_t rev = (uint32_t)mcp->mcp_rev;
1498 !X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_E)) {