Cross Reference: /illumos-gate/usr/src/uts/intel/io/drm/radeon

Lines Matching defs:sarea_priv
763 	x += dev_priv->sarea_priv->boxes[0].x1;
764 	y += dev_priv->sarea_priv->boxes[0].y1;
863 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
865 	int nbox = sarea_priv->nbox;
866 	drm_clip_rect_t *pbox = sarea_priv->boxes;
901 		dev_priv->sarea_priv->ctx_owner = 0;
981 		dev_priv->sarea_priv->ctx_owner = 0;
1269 		dev_priv->sarea_priv->ctx_owner = 0;
1277 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1343 		dev_priv->sarea_priv->ctx_owner = 0;
1351 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1388 	dev_priv->sarea_priv->last_clear++;
1392 	RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
1401 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1402 	int nbox = sarea_priv->nbox;
1403 	drm_clip_rect_t *pbox = sarea_priv->boxes;
1464 	dev_priv->sarea_priv->last_frame ++;
1468 	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1483 	    dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
1499 	    dev_priv->sarea_priv->crtc2_base + offset);
1508 	dev_priv->sarea_priv->last_frame ++;
1509 	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1514 	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1555 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1558 	int nbox = sarea_priv->nbox;
1575 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1602 	buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1652 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1659 	int nbox = sarea_priv->nbox;
1692 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
2216 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2242 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2243 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2246 	    sarea_priv->nbox * sizeof (depth_boxes[0])))
2275 	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
2323 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2329 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2330 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2333 	dev_priv->sarea_priv->ctx_owner = 0;
2344 	drm_radeon_sarea_t *sarea_priv;
2357 	sarea_priv = dev_priv->sarea_priv;
2395 		if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2397 			    &sarea_priv->context_state,
2398 			    sarea_priv->tex_state,
2399 			    sarea_priv->dirty)) {
2404 			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2414 		prim.vc_format = dev_priv->sarea_priv->vc_format;
2432 	drm_radeon_sarea_t *sarea_priv;
2445 	sarea_priv = dev_priv->sarea_priv;
2491 	if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2493 		    &sarea_priv->context_state,
2494 		    sarea_priv->tex_state,
2495 		    sarea_priv->dirty)) {
2500 		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2514 	prim.vc_format = dev_priv->sarea_priv->vc_format;
2703 	drm_radeon_sarea_t *sarea_priv;
2717 	sarea_priv = dev_priv->sarea_priv;
2765 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2807 		if (sarea_priv->nbox == 1)
2808 			sarea_priv->nbox = 0;
3389 			dev_priv->sarea_priv->tiling_enabled = 0;
3394 			dev_priv->sarea_priv->tiling_enabled = 1;