Lines Matching defs:ring
1051 dev_priv->ring.tail = cur_read_ptr;
1113 /* Reset the CP ring */
1164 /* Initialize the ring buffer's read and write pointers */
1168 dev_priv->ring.tail = cur_read_ptr;
1186 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1191 /* Set ring buffer size */
1194 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1196 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1207 * We simply put this behind the ring read pointer, this works
1411 * We don't support anything other than bus-mastering ring mode,
1412 * but the ring can be in either AGP or PCI space for the ring
1494 DRM_ERROR("could not find cp ring region, offset=0x%lx\n",
1501 DRM_ERROR("could not find ring read pointer, offset=0x%lx\n",
1640 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1641 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle +
1643 dev_priv->ring.size = init->ring_size;
1644 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1646 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof (u32)) - 1;
1648 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1985 /* Just reset the CP ring. Called as part of an X Server engine reset. */
2172 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2179 ring->space = (head - ring->tail) * sizeof (u32);
2180 if (ring->space <= 0)
2181 ring->space += ring->size;
2182 if (ring->space > n)