Lines Matching defs:mmu
91 struct hat_mmu_info mmu;
228 sizeof (pgcnt_t) * (mmu.max_page_level + 1));
281 use_vlp = mmu.pae_hat;
293 hat->hat_num_hash = mmu.vlp_hash_cnt;
296 hat->hat_num_hash = mmu.hash_cnt;
357 xen_pin(hat->hat_htable->ht_pfn, mmu.max_level);
359 xen_pin(hat->hat_user_ptable, mmu.max_level);
511 mmu.max_page_level = lvl;
514 mmu.umax_page_level = 1;
516 mmu.umax_page_level = lvl;
536 mmu.pt_global = PT_GLOBAL;
541 mmu.pae_hat = kbm_pae_support;
543 mmu.pt_nx = PT_NX;
545 mmu.pt_nx = 0;
553 mmu.hole_start = (1ul << (va_bits - 1));
554 mmu.hole_end = 0ul - mmu.hole_start - 1;
556 mmu.hole_end = 0;
557 mmu.hole_start = mmu.hole_end - 1;
562 * contains the value to be subtracted from mmu.hole_start.
565 hole_start = mmu.hole_start - hole_start;
567 hole_start = mmu.hole_start;
569 hole_end = mmu.hole_end;
571 mmu.highest_pfn = mmu_btop((1ull << pa_bits) - 1);
572 if (mmu.pae_hat == 0 && pa_bits > 32)
573 mmu.highest_pfn = PFN_4G - 1;
575 if (mmu.pae_hat) {
576 mmu.pte_size = 8; /* 8 byte PTEs */
577 mmu.pte_size_shift = 3;
579 mmu.pte_size = 4; /* 4 byte PTEs */
580 mmu.pte_size_shift = 2;
583 if (mmu.pae_hat && !is_x86_feature(x86_featureset, X86FSET_PAE))
591 mmu.num_level = 4;
592 mmu.max_level = 3;
593 mmu.ptes_per_table = 512;
594 mmu.top_level_count = 512;
596 mmu.level_shift[0] = 12;
597 mmu.level_shift[1] = 21;
598 mmu.level_shift[2] = 30;
599 mmu.level_shift[3] = 39;
603 if (mmu.pae_hat) {
604 mmu.num_level = 3;
605 mmu.max_level = 2;
606 mmu.ptes_per_table = 512;
607 mmu.top_level_count = 4;
609 mmu.level_shift[0] = 12;
610 mmu.level_shift[1] = 21;
611 mmu.level_shift[2] = 30;
614 mmu.num_level = 2;
615 mmu.max_level = 1;
616 mmu.ptes_per_table = 1024;
617 mmu.top_level_count = 1024;
619 mmu.level_shift[0] = 12;
620 mmu.level_shift[1] = 22;
625 for (i = 0; i < mmu.num_level; ++i) {
626 mmu.level_size[i] = 1UL << mmu.level_shift[i];
627 mmu.level_offset[i] = mmu.level_size[i] - 1;
628 mmu.level_mask[i] = ~mmu.level_offset[i];
633 mmu_page_sizes = mmu.max_page_level + 1;
634 mmu_exported_page_sizes = mmu.umax_page_level + 1;
641 for (i = 0; i <= mmu.max_page_level; ++i) {
642 mmu.pte_bits[i] = PT_VALID | pt_kern;
644 mmu.pte_bits[i] |= PT_PAGESIZE;
650 for (i = 1; i < mmu.num_level; ++i)
651 mmu.ptp_bits[i] = PT_PTPBITS;
654 mmu.ptp_bits[2] = PT_VALID;
663 max_htables = physmax / mmu.ptes_per_table;
664 mmu.hash_cnt = MMU_PAGESIZE / sizeof (htable_t *);
665 while (mmu.hash_cnt > 16 && mmu.hash_cnt >= max_htables)
666 mmu.hash_cnt >>= 1;
667 mmu.vlp_hash_cnt = mmu.hash_cnt;
676 while (mmu.hash_cnt * HASH_MAX_LENGTH < max_htables)
677 mmu.hash_cnt <<= 1;
712 mmu.hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL,
718 if (mmu.hash_cnt == mmu.vlp_hash_cnt) {
722 mmu.vlp_hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL,
751 kas.a_hat->hat_num_hash = mmu.hash_cnt;
753 bzero(kas.a_hat->hat_ht_hash, mmu.hash_cnt * sizeof (htable_t *));
872 if (mmu.pae_hat) {
902 if (rp->hkr_level <= mmu.max_page_level &&
921 if (mmu.pae_hat) {
963 ASSERT(mmu.pae_hat);
1076 PTE_SET(pte, mmu.pt_nx);
1218 for (l = 0; l <= mmu.max_page_level; l++)
1479 PTE_SET(pte, mmu.pt_global);
1507 pgcnt_t pg_off = mmu_btop(va - mmu.kmap_addr);
1518 PTE_SET(pte, mmu.pt_global);
1523 if (mmu.pae_hat)
1524 pte_ptr = mmu.kmap_ptes + pg_off;
1526 pte_ptr = (x86pte32_t *)mmu.kmap_ptes + pg_off;
1527 ht = mmu.kmap_htables[(va - mmu.kmap_htables[0]->ht_vaddr) >>
1598 if (mmu.kmap_addr <= va && va < mmu.kmap_eaddr) {
1663 for (level = mmu.max_page_level; ; --level) {
1792 for (level = mmu.max_page_level; ; --level) {
1980 if (mmu.max_level == 2)
2288 pg_index = mmu_btop(va - mmu.kmap_addr);
2289 pte_ptr = PT_INDEX_PTR(mmu.kmap_ptes, pg_index);
2295 ht = mmu.kmap_htables[(va - mmu.kmap_htables[0]->ht_vaddr)
2321 if (mmu.kmap_addr <= va && va < mmu.kmap_eaddr) {
2448 ASSERT(ht->ht_level <= mmu.max_page_level);
2602 ht = htable_getpte(hat, vaddr, NULL, &pte, mmu.max_page_level);
2616 if (!PTE_GET(pte, mmu.pt_nx))
2672 if ((attr & PROT_EXEC) && PTE_GET(oldpte, mmu.pt_nx))
2673 newpte &= ~mmu.pt_nx;
2685 if (!(attr & PROT_EXEC) && !PTE_GET(oldpte, mmu.pt_nx))
2686 newpte |= mmu.pt_nx;
2697 if ((attr & PROT_EXEC) && !PTE_GET(oldpte, mmu.pt_nx))
2698 newpte |= mmu.pt_nx;
2812 if (mmu.kmap_addr <= vaddr && vaddr < mmu.kmap_eaddr) {
2816 pg_index = mmu_btop(vaddr - mmu.kmap_addr);
2817 pte = GET_PTE(PT_INDEX_PTR(mmu.kmap_ptes, pg_index));
2862 if (mmu.kmap_addr <= vaddr && vaddr < mmu.kmap_eaddr) {
2863 pg_off = mmu_btop(vaddr - mmu.kmap_addr);
2864 if (mmu.pae_hat)
2865 return (PTE_ISVALID(mmu.kmap_ptes[pg_off]));
2868 ((x86pte32_t *)mmu.kmap_ptes)[pg_off]));
2975 if (l == mmu.max_level)
3124 l = mmu.max_page_level;
3125 if (l == mmu.max_level)
3844 * Setup the given brand new hat structure as the new HAT on this cpu's mmu.
3931 (pte_pa & MMU_PAGEOFFSET) >> mmu.pte_size_shift, NULL);
3932 if (mmu.pae_hat)
3992 (pte_pa & MMU_PAGEOFFSET) >> mmu.pte_size_shift, NULL);
3993 if (mmu.pae_hat)
4074 ASSERT(level <= mmu.max_page_level);
4473 *pte_ma = base_ma + (entry << mmu.pte_size_shift);