Lines Matching refs:CPU
164 * Initialize the platform type from CPU 0 to ensure that
176 * of the boot CPU. Note that if we choose to support CPUs that have
190 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves
197 * zero, regardless of CPU type; however, we do not expect hypervisors
202 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
203 cpuid_getfamily(CPU) == 6 &&
204 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
231 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
232 cpuid_getfamily(CPU) <= 0xf &&
235 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
236 cpuid_getfamily(CPU) <= 6 &&
253 patch_memops(cpuid_getvendor(CPU));
306 THREAD_ONPROC(&t0, CPU);
328 CPU->cpu_thread = &t0;
330 CPU->cpu_disp = &cpu0_disp;
331 CPU->cpu_disp->disp_cpu = CPU;
332 CPU->cpu_dispthread = &t0;
333 CPU->cpu_idle_thread = &t0;
334 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
335 CPU->cpu_dispatch_pri = t0.t_pri;
337 CPU->cpu_id = 0;
339 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
350 init_cpu_mstate(CPU, CMS_SYSTEM);
355 cpu_list_init(CPU);
357 pg_cpu_bootstrap(CPU);
361 * active CPU list it's time to inform kmdb if present.
383 cpu_vm_data_init(CPU);
400 /* Only enable CPU/memory DR on 64 bits kernel. */
425 * support CPU DR operations.
469 ucode_check(CPU);
471 if (workaround_errata(CPU) != 0)