Lines Matching defs:ecx
308 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
324 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */
337 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
455 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
683 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum
1031 * - ignore %ecx feature word
1054 * We don't currently depend on any of the %ecx
1235 * In addition to ecx and edx, Intel is storing a bunch of instruction
1783 * CPUID function 4 expects %ecx to be initialized
1786 * with %ecx set to 0, 1, 2, ... until it returns with
1791 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
1794 * Note: we need to explicitly initialize %ecx here, since
2142 * up w.r.t. encoding cache sizes in %ecx
2573 * references the regs for fn 4, %ecx == 0, which
2583 * for function 4, %ecx == 1 .. cpi_std_4_size.
2585 * The regs for fn 4, %ecx == 0 has already
2700 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
2704 *ecx = CPI_FEATURES_ECX(cpi);
2722 *ecx &= ~CPUID_INTC_ECX_SSE3;
2725 *ecx &= ~CPUID_INTC_ECX_SSSE3;
2727 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
2729 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
2731 *ecx &= ~CPUID_INTC_ECX_AES;
2733 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
2735 *ecx &= ~(CPUID_INTC_ECX_XSAVE |
2738 *ecx &= ~CPUID_INTC_ECX_AVX;
2740 *ecx &= ~CPUID_INTC_ECX_F16C;
2742 *ecx &= ~CPUID_INTC_ECX_FMA;
2770 if (*ecx & CPUID_INTC_ECX_SSE3)
2772 if (*ecx & CPUID_INTC_ECX_SSSE3)
2774 if (*ecx & CPUID_INTC_ECX_SSE4_1)
2776 if (*ecx & CPUID_INTC_ECX_SSE4_2)
2778 if (*ecx & CPUID_INTC_ECX_MOVBE)
2780 if (*ecx & CPUID_INTC_ECX_AES)
2782 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
2784 if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
2785 (*ecx & CPUID_INTC_ECX_OSXSAVE)) {
2788 if (*ecx & CPUID_INTC_ECX_AVX) {
2790 if (*ecx & CPUID_INTC_ECX_F16C)
2792 if (*ecx & CPUID_INTC_ECX_FMA)
2802 if (*ecx & CPUID_INTC_ECX_VMX)
2804 if (*ecx & CPUID_INTC_ECX_POPCNT)
2817 if (*ecx & CPUID_INTC_ECX_CX16)
2820 if (*ecx & CPUID_INTC_ECX_RDRAND)
2834 uint32_t *edx, *ecx;
2847 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
2850 *ecx = CPI_FEATURES_XTD_ECX(cpi);
2865 *ecx &= ~CPUID_AMD_ECX_SSE4A;
2899 if (*ecx & CPUID_AMD_ECX_SVM)
2906 if (*ecx & CPUID_AMD_ECX_AHF64)
2908 if (*ecx & CPUID_AMD_ECX_SSE4A)
2910 if (*ecx & CPUID_AMD_ECX_LZCNT)
2921 if (*ecx & CPUID_INTC_ECX_AHF64)
4380 /* cpuid-features-ecx */
4394 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
4413 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));