Lines Matching refs:hdlp
159 pci_get_priority(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, int *pri)
163 DDI_INTR_NEXDBG((CE_CONT, "pci_get_priority: dip = 0x%p, hdlp = %p\n",
164 (void *)dip, (void *)hdlp));
167 hdlp->ih_inum)) == NULL) {
168 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type)) {
170 pci_common_set_parent_private_data(hdlp->ih_dip);
172 hdlp->ih_inum);
191 ddi_intr_handle_impl_t *hdlp, void *result)
216 (void *)pdip, (void *)rdip, intr_op, (void *)hdlp));
299 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type)) {
300 if (pci_msi_get_nintrs(hdlp->ih_dip, hdlp->ih_type,
304 *(int *)result = i_ddi_get_intx_nintrs(hdlp->ih_dip);
314 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
315 return (pci_alloc_intr_fixed(pdip, rdip, hdlp, result));
319 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type) &&
321 (pci_get_priority(rdip, hdlp, &priority) == DDI_SUCCESS)) {
328 hdlp->ih_pri =
332 hdlp->ih_pri = priority;
333 behavior = (int)(uintptr_t)hdlp->ih_scratch2;
347 if (hdlp->ih_type == DDI_INTR_TYPE_MSI)
349 else if (hdlp->ih_type == DDI_INTR_TYPE_MSIX)
372 (void) (*psm_intr_ops)(rdip, hdlp,
380 (*(int *)result < hdlp->ih_scratch1)) {
384 hdlp->ih_scratch1 = *(int *)result;
385 (void) (*psm_intr_ops)(rdip, hdlp,
390 if (hdlp->ih_type == DDI_INTR_TYPE_MSIX) {
391 if (!(msix_p = i_ddi_get_msix(hdlp->ih_dip))) {
392 msix_p = pci_msix_init(hdlp->ih_dip);
394 i_ddi_set_msix(hdlp->ih_dip,
402 hdlp->ih_inum));
405 hdlp,
417 (int)hdlp->ih_inum);
420 ispec->intrspec_pri = hdlp->ih_pri;
428 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type) &&
430 if (i_ddi_intr_get_current_nintrs(hdlp->ih_dip) - 1 ==
441 (void) (*psm_intr_ops)(rdip, hdlp,
444 if (hdlp->ih_type == DDI_INTR_TYPE_MSIX) {
445 msix_p = i_ddi_get_msix(hdlp->ih_dip);
448 hdlp->ih_dip) - 1) == 0) {
450 i_ddi_set_msix(hdlp->ih_dip, NULL);
453 } else if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) {
454 return (pci_free_intr_fixed(pdip, rdip, hdlp));
460 if (pci_get_priority(rdip, hdlp, &priority) != DDI_SUCCESS)
475 isp = pci_intx_get_ispec(pdip, rdip, (int)hdlp->ih_inum);
481 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) {
483 ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec;
484 psm_rval = (*psm_intr_ops)(rdip, hdlp,
503 if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_PRI, result) ==
512 isp = pci_intx_get_ispec(pdip, rdip, (int)hdlp->ih_inum);
515 ispec->intrspec_func = hdlp->ih_cb_func;
516 ihdl_plat_datap = (ihdl_plat_t *)hdlp->ih_private;
517 pci_kstat_create(&ihdl_plat_datap->ip_ksp, pdip, hdlp);
522 isp = pci_intx_get_ispec(pdip, rdip, (int)hdlp->ih_inum);
526 ihdl_plat_datap = (ihdl_plat_t *)hdlp->ih_private;
536 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type))
537 pci_rval = pci_msi_get_cap(rdip, hdlp->ih_type,
539 else if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
544 psm_rval = (*psm_intr_ops)(rdip, hdlp,
571 if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_CAP, result)) {
582 if (pci_enable_intr(pdip, rdip, hdlp, hdlp->ih_inum) !=
587 "vector=0x%x\n", hdlp->ih_vector));
594 pci_disable_intr(pdip, rdip, hdlp, hdlp->ih_inum);
596 "vector = %x\n", hdlp->ih_vector));
601 if (hdlp->ih_type != DDI_INTR_TYPE_MSI) {
610 count = hdlp->ih_scratch1;
611 h_array = (ddi_intr_handle_t *)hdlp->ih_scratch2;
613 hdlp = (ddi_intr_handle_impl_t *)h_array[i];
614 if (pci_enable_intr(pdip, rdip, hdlp,
615 hdlp->ih_inum) != DDI_SUCCESS) {
619 hdlp = (ddi_intr_handle_impl_t *)
621 pci_disable_intr(pdip, rdip, hdlp,
622 hdlp->ih_inum);
627 "BLOCKENABLE inum %x done\n", hdlp->ih_inum));
633 if (hdlp->ih_type != DDI_INTR_TYPE_MSI) {
642 count = hdlp->ih_scratch1;
643 h_array = (ddi_intr_handle_t *)hdlp->ih_scratch2;
645 hdlp = (ddi_intr_handle_impl_t *)h_array[i];
646 pci_disable_intr(pdip, rdip, hdlp, hdlp->ih_inum);
648 "BLOCKDISABLE inum %x done\n", hdlp->ih_inum));
657 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type))
659 hdlp->ih_type, hdlp->ih_inum);
660 else if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
663 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type))
665 hdlp->ih_type, hdlp->ih_inum);
666 else if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
671 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
675 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED &&
682 psm_rval = (*psm_intr_ops)(rdip, hdlp,
690 psm_rval = (*psm_intr_ops)(rdip, hdlp,
693 psm_rval = (*psm_intr_ops)(rdip, hdlp,
702 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type))
703 pci_rval = pci_msi_get_pending(rdip, hdlp->ih_type,
704 hdlp->ih_inum, &pci_status);
705 else if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
710 psm_rval = (*psm_intr_ops)(rdip, hdlp,
732 bcopy(hdlp, &tmp_hdl, sizeof (ddi_intr_handle_impl_t));
743 "vector = 0x%x, cpu = 0x%x\n", hdlp->ih_vector,
749 bcopy(hdlp, &tmp_hdl, sizeof (ddi_intr_handle_impl_t));
757 hdlp->ih_vector = tmp_hdl.ih_vector;
759 "vector = 0x%x\n", hdlp->ih_vector));
765 if (apix_irm_pool_p && DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type)) {
771 return (i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result));
782 ddi_intr_handle_impl_t *hdlp, void *result)
798 hdlp->ih_cap |= pci_status;
809 (int)hdlp->ih_inum);
812 if (hdlp->ih_private == NULL) { /* allocate phdl structure */
814 i_ddi_alloc_intr_phdl(hdlp);
816 ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec;
817 ret = (*psm_intr_ops)(rdip, hdlp,
821 i_ddi_free_intr_phdl(hdlp);
822 hdlp->ih_private = NULL;
841 ddi_intr_handle_impl_t *hdlp)
860 (int)hdlp->ih_inum);
863 ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec;
864 ret = (*psm_intr_ops)(rdip, hdlp,
921 ddi_intr_handle_impl_t *hdlp, uint32_t inum)
925 ihdl_plat_t *ihdl_plat_datap = (ihdl_plat_t *)hdlp->ih_private;
927 DDI_INTR_NEXDBG((CE_CONT, "pci_enable_intr: hdlp %p inum %x\n",
928 (void *)hdlp, inum));
934 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type)) {
936 ispec->intrspec_pri = hdlp->ih_pri;
941 if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_XLATE_VECTOR, &irq) ==
945 hdlp->ih_pri, irq));
948 if (!add_avintr((void *)hdlp, hdlp->ih_pri, hdlp->ih_cb_func,
949 DEVI(rdip)->devi_name, irq, hdlp->ih_cb_arg1,
950 hdlp->ih_cb_arg2, &ihdl_plat_datap->ip_ticks, rdip))
953 hdlp->ih_vector = irq;
961 ddi_intr_handle_impl_t *hdlp, uint32_t inum)
965 ihdl_plat_t *ihdl_plat_datap = (ihdl_plat_t *)hdlp->ih_private;
971 if (DDI_INTR_IS_MSI_OR_MSIX(hdlp->ih_type)) {
973 ispec->intrspec_pri = hdlp->ih_pri;
978 (void) (*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_XLATE_VECTOR, &irq);
981 rem_avintr((void *)hdlp, hdlp->ih_pri, hdlp->ih_cb_func, irq);
1106 ddi_acc_hdl_t *hdlp = (ddi_acc_hdl_t *)in_args->handle;
1145 if (hdlp->ah_acc.devacc_attr_endian_flags ==
1204 if (hdlp->ah_acc.devacc_attr_endian_flags ==
1324 ddi_acc_hdl_t *hdlp = (ddi_acc_hdl_t *)in_args->handle;
1360 if (hdlp->ah_acc.devacc_attr_endian_flags ==
1419 if (hdlp->ah_acc.devacc_attr_endian_flags ==
1499 pci_config_rd8(ddi_acc_impl_t *hdlp, uint8_t *addr)
1509 cfp = (pci_acc_cfblk_t *)&hdlp->ahi_common.ah_bus_private;
1518 pci_config_rep_rd8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
1528 *h++ = pci_config_rd8(hdlp, d++);
1531 *h++ = pci_config_rd8(hdlp, d);
1535 pci_config_rd16(ddi_acc_impl_t *hdlp, uint16_t *addr)
1545 cfp = (pci_acc_cfblk_t *)&hdlp->ahi_common.ah_bus_private;
1554 pci_config_rep_rd16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1564 *h++ = pci_config_rd16(hdlp, d++);
1567 *h++ = pci_config_rd16(hdlp, d);
1571 pci_config_rd32(ddi_acc_impl_t *hdlp, uint32_t *addr)
1581 cfp = (pci_acc_cfblk_t *)&hdlp->ahi_common.ah_bus_private;
1590 pci_config_rep_rd32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1600 *h++ = pci_config_rd32(hdlp, d++);
1603 *h++ = pci_config_rd32(hdlp, d);
1608 pci_config_wr8(ddi_acc_impl_t *hdlp, uint8_t *addr, uint8_t value)
1617 cfp = (pci_acc_cfblk_t *)&hdlp->ahi_common.ah_bus_private;
1624 pci_config_rep_wr8(ddi_acc_impl_t *hdlp, uint8_t *host_addr,
1634 pci_config_wr8(hdlp, d++, *h++);
1637 pci_config_wr8(hdlp, d, *h++);
1641 pci_config_wr16(ddi_acc_impl_t *hdlp, uint16_t *addr, uint16_t value)
1650 cfp = (pci_acc_cfblk_t *)&hdlp->ahi_common.ah_bus_private;
1657 pci_config_rep_wr16(ddi_acc_impl_t *hdlp, uint16_t *host_addr,
1667 pci_config_wr16(hdlp, d++, *h++);
1670 pci_config_wr16(hdlp, d, *h++);
1674 pci_config_wr32(ddi_acc_impl_t *hdlp, uint32_t *addr, uint32_t value)
1683 cfp = (pci_acc_cfblk_t *)&hdlp->ahi_common.ah_bus_private;
1690 pci_config_rep_wr32(ddi_acc_impl_t *hdlp, uint32_t *host_addr,
1700 pci_config_wr32(hdlp, d++, *h++);
1703 pci_config_wr32(hdlp, d, *h++);
1707 pci_config_rd64(ddi_acc_impl_t *hdlp, uint64_t *addr)
1715 lw_val = pci_config_rd32(hdlp, dp);
1717 hi_val = pci_config_rd32(hdlp, dp);
1723 pci_config_wr64(ddi_acc_impl_t *hdlp, uint64_t *addr, uint64_t value)
1732 pci_config_wr32(hdlp, dp, lw_val);
1734 pci_config_wr32(hdlp, dp, hi_val);
1738 pci_config_rep_rd64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
1743 *host_addr++ = pci_config_rd64(hdlp, dev_addr++);
1746 *host_addr++ = pci_config_rd64(hdlp, dev_addr);
1751 pci_config_rep_wr64(ddi_acc_impl_t *hdlp, uint64_t *host_addr,
1756 pci_config_wr64(hdlp, host_addr++, *dev_addr++);
1759 pci_config_wr64(hdlp, host_addr++, *dev_addr);