Lines Matching refs:state
108 ioat_channel_init(ioat_state_t *state)
113 * initialize each dma channel's state which doesn't change across
116 state->is_chansize = sizeof (struct ioat_channel_s) *
117 state->is_num_channels;
118 state->is_channel = kmem_zalloc(state->is_chansize, KM_SLEEP);
119 for (i = 0; i < state->is_num_channels; i++) {
120 state->is_channel[i].ic_state = state;
121 state->is_channel[i].ic_regs = (uint8_t *)
122 ((uintptr_t)state->is_genregs +
126 /* initial the allocator (from 0 to state->is_num_channels) */
127 ioat_rs_init(state, 0, state->is_num_channels, &state->is_channel_rs);
137 ioat_channel_fini(ioat_state_t *state)
139 ioat_rs_fini(&state->is_channel_rs);
140 kmem_free(state->is_channel, state->is_chansize);
158 ioat_state_t *state;
165 state = (ioat_state_t *)device_private;
169 e = ioat_rs_alloc(state->is_channel_rs, &chan_num);
174 channel = &state->is_channel[chan_num];
177 channel->ic_ver = state->is_ver;
187 reg = ddi_get16(state->is_reg_handle,
201 ddi_put16(state->is_reg_handle,
205 estat = ddi_get32(state->is_reg_handle,
212 ddi_put32(state->is_reg_handle,
233 state->is_instance, channel->ic_chan_num);
245 info->qc_id = state->is_deviceinfo.di_id;
246 info->qc_capabilities = (uint64_t)state->is_capabilities;
277 ioat_channel_suspend(ioat_state_t *state)
293 ioat_channel_resume(ioat_state_t *state)
301 for (i = 0; i < state->is_num_channels; i++) {
302 channel = &state->is_channel[i];
316 ddi_put16(state->is_reg_handle,
320 estat = ddi_get32(state->is_reg_handle,
327 ddi_put32(state->is_reg_handle,
336 ddi_put32(state->is_reg_handle,
339 ddi_put32(state->is_reg_handle,
344 ddi_put32(state->is_reg_handle,
347 ddi_put32(state->is_reg_handle,
355 ddi_put32(state->is_reg_handle,
358 ddi_put32(state->is_reg_handle,
381 ioat_channel_quiesce(ioat_state_t *state)
388 for (i = 0; i < state->is_num_channels; i++) {
390 ioat_channel_t channel = state->is_channel + i;
396 ddi_put16(state->is_reg_handle,
413 ioat_state_t *state;
420 state = channel->ic_state;
424 ddi_put16(state->is_reg_handle,
439 ioat_rs_free(state->is_channel_rs, chan_num);
451 ioat_state_t *state;
457 state = channel->ic_state;
460 status = ddi_get32(state->is_reg_handle,
464 status = ddi_get32(state->is_reg_handle,
470 chanerr = ddi_get32(state->is_reg_handle,
485 chanctrl = ddi_get16(state->is_reg_handle,
487 ddi_put16(state->is_reg_handle,
489 (void) ddi_get16(state->is_reg_handle,
523 ioat_state_t *state;
525 state = channel->ic_state;
529 ddi_put8(state->is_reg_handle,
533 ddi_put8(state->is_reg_handle,
545 ioat_state_t *state;
551 state = channel->ic_state;
557 e = ddi_dma_alloc_handle(state->is_dip, &ioat_cmpl_dma_attr,
585 ddi_put32(state->is_reg_handle,
588 ddi_put32(state->is_reg_handle,
609 ioat_state_t *state;
611 state = channel->ic_state;
614 ddi_put32(state->is_reg_handle,
616 ddi_put32(state->is_reg_handle,
632 ioat_state_t *state;
638 state = channel->ic_state;
655 e = ddi_dma_alloc_handle(state->is_dip, &ioat_desc_dma_attr,
690 ddi_put32(state->is_reg_handle,
693 ddi_put32(state->is_reg_handle,
698 ddi_put32(state->is_reg_handle,
701 ddi_put32(state->is_reg_handle,
727 ioat_state_t *state;
730 state = channel->ic_state;
734 ddi_put32(state->is_reg_handle,
736 ddi_put32(state->is_reg_handle,
740 ddi_put32(state->is_reg_handle,
742 ddi_put32(state->is_reg_handle,
768 ioat_state_t *state;
771 state = channel->ic_state;
774 /* init the completion state */
778 /* write in the descriptor and init the descriptor state */
787 ddi_put8(state->is_reg_handle,
806 ddi_put16(state->is_reg_handle,
901 /* setup the dcopy and ioat private state pointers */
963 ioat_state_t *state;
979 state = channel->ic_state;
1082 /* save away the state so we can poll on it. */
1100 ddi_put8(state->is_reg_handle,
1105 ddi_put16(state->is_reg_handle,
1142 * channel, set CONTEXT_CHANGE bit and dca id, set dca state to active,