Lines Matching refs:state
99 static int ioat_chip_init(ioat_state_t *state);
100 static void ioat_chip_fini(ioat_state_t *state);
101 static int ioat_drv_init(ioat_state_t *state);
102 static void ioat_drv_fini(ioat_state_t *state);
104 static void ioat_intr_enable(ioat_state_t *state);
105 static void ioat_intr_disable(ioat_state_t *state);
106 void ioat_detach_finish(ioat_state_t *state);
184 ioat_state_t *state;
195 state = ddi_get_soft_state(ioat_statep, instance);
196 if (state == NULL) {
199 e = ioat_channel_resume(state);
203 ioat_intr_enable(state);
215 state = ddi_get_soft_state(ioat_statep, instance);
216 if (state == NULL) {
220 state->is_dip = dip;
221 state->is_instance = instance;
224 e = ioat_chip_init(state);
229 /* initialize driver state, must be after chip init */
230 e = ioat_drv_init(state);
243 ioat_intr_enable(state);
249 e = dcopy_device_register(state, &state->is_deviceinfo,
250 &state->is_device_handle);
258 ioat_intr_disable(state);
261 ioat_drv_fini(state);
263 ioat_chip_fini(state);
277 ioat_state_t *state;
283 state = ddi_get_soft_state(ioat_statep, instance);
284 if (state == NULL) {
293 ioat_channel_suspend(state);
305 e = dcopy_device_unregister(&state->is_device_handle);
314 ioat_detach_finish(state);
326 ioat_state_t *state;
337 state = ddi_get_soft_state(ioat_statep, instance);
338 if (state == NULL) {
341 *result = (void *)state->is_dip;
366 ioat_state_t *state;
370 state = ddi_get_soft_state(ioat_statep, instance);
371 if (state == NULL) {
394 ioat_chip_init(ioat_state_t *state)
404 e = ddi_regs_map_setup(state->is_dip, 1, (caddr_t *)&state->is_genregs,
405 0, 0, &attr, &state->is_reg_handle);
411 state->is_num_channels = (uint_t)ddi_get8(state->is_reg_handle,
412 &state->is_genregs[IOAT_CHANCNT]);
418 if (state->is_num_channels == 0) {
422 state->is_maxxfer = (uint_t)ddi_get8(state->is_reg_handle,
423 &state->is_genregs[IOAT_XFERCAP]);
424 state->is_chanoff = (uintptr_t)ddi_get16(state->is_reg_handle,
425 (uint16_t *)&state->is_genregs[IOAT_PERPORT_OFF]);
426 state->is_cbver = (uint_t)ddi_get8(state->is_reg_handle,
427 &state->is_genregs[IOAT_CBVER]);
428 state->is_intrdelay = (uint_t)ddi_get16(state->is_reg_handle,
429 (uint16_t *)&state->is_genregs[IOAT_INTRDELAY]);
430 state->is_status = (uint_t)ddi_get16(state->is_reg_handle,
431 (uint16_t *)&state->is_genregs[IOAT_CSSTATUS]);
432 state->is_capabilities = (uint_t)ddi_get32(state->is_reg_handle,
433 (uint32_t *)&state->is_genregs[IOAT_DMACAPABILITY]);
435 if (state->is_cbver & 0x10) {
436 state->is_ver = IOAT_CBv1;
437 } else if (state->is_cbver & 0x20) {
438 state->is_ver = IOAT_CBv2;
447 ddi_regs_map_free(&state->is_reg_handle);
457 ioat_chip_fini(ioat_state_t *state)
459 ddi_regs_map_free(&state->is_reg_handle);
467 ioat_drv_init(ioat_state_t *state)
473 mutex_init(&state->is_mutex, NULL, MUTEX_DRIVER, NULL);
475 state->is_deviceinfo.di_dip = state->is_dip;
476 state->is_deviceinfo.di_num_dma = state->is_num_channels;
477 state->is_deviceinfo.di_maxxfer = state->is_maxxfer;
478 state->is_deviceinfo.di_capabilities = state->is_capabilities;
479 state->is_deviceinfo.di_cb = &ioat_cb;
481 e = pci_config_setup(state->is_dip, &handle);
487 state->is_deviceinfo.di_id = (uint64_t)pci_config_get16(handle, 0);
488 state->is_deviceinfo.di_id = state->is_deviceinfo.di_id << 16;
491 state->is_deviceinfo.di_id |= (uint64_t)pci_config_get16(handle, 2);
492 state->is_deviceinfo.di_id = state->is_deviceinfo.di_id << 32;
495 state->is_deviceinfo.di_id |= (uint64_t)state->is_cbver;
498 e = ddi_intr_hilevel(state->is_dip, 0);
505 e = ddi_add_intr(state->is_dip, 0, NULL, NULL, ioat_isr,
506 (caddr_t)state);
511 e = ddi_get_iblock_cookie(state->is_dip, 0, &state->is_iblock_cookie);
516 e = ioat_channel_init(state);
525 ddi_remove_intr(state->is_dip, 0, state->is_iblock_cookie);
529 mutex_destroy(&state->is_mutex);
539 ioat_drv_fini(ioat_state_t *state)
541 ioat_channel_fini(state);
542 ddi_remove_intr(state->is_dip, 0, state->is_iblock_cookie);
543 mutex_destroy(&state->is_mutex);
553 ioat_state_t *state;
556 state = device_private;
564 ioat_detach_finish(state);
572 ioat_detach_finish(ioat_state_t *state)
574 ioat_intr_disable(state);
575 ddi_remove_minor_node(state->is_dip, NULL);
576 ioat_drv_fini(state);
577 ioat_chip_fini(state);
578 (void) ddi_soft_state_free(ioat_statep, state->is_instance);
586 ioat_intr_enable(ioat_state_t *state)
592 intr_status = ddi_get32(state->is_reg_handle,
593 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS]);
595 ddi_put32(state->is_reg_handle,
596 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS],
601 ddi_put8(state->is_reg_handle, &state->is_genregs[IOAT_INTRCTL],
610 ioat_intr_disable(ioat_state_t *state)
616 (void) ddi_get8(state->is_reg_handle,
617 &state->is_genregs[IOAT_INTRCTL]);
628 ioat_state_t *state;
634 state = (ioat_state_t *)parm;
636 intrctrl = ddi_get8(state->is_reg_handle,
637 &state->is_genregs[IOAT_INTRCTL]);
644 ddi_put8(state->is_reg_handle,
645 &state->is_genregs[IOAT_INTRCTL], intrctrl);
650 intr_status = ddi_get32(state->is_reg_handle,
651 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS]);
656 for (i = 0; i < state->is_num_channels; i++) {
658 ioat_channel_intr(&state->is_channel[i]);
671 ddi_put8(state->is_reg_handle, &state->is_genregs[IOAT_INTRCTL],
680 ioat_state_t *state;
684 state = ddi_get_soft_state(ioat_statep, instance);
685 if (state == NULL) {
689 ioat_intr_disable(state);
690 ioat_channel_quiesce(state);