Cross Reference: /illumos-gate/usr/src/uts/common/sys/pcie

Lines Matching refs:bus_p
59 #define	PCIE_BUS2DIP(bus_p) bus_p->bus_dip
60 #define	PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p))
61 #define	PCIE_BUS2DOM(bus_p) bus_p->bus_dom
65  * These macros depend on initialization of type related data in bus_p.
67 #define	PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off)
68 #define	PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off)
69 #define	PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p))
70 #define	PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off)
72 #define	PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p))
86 #define	PCIE_IS_RC(bus_p) \
87 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO)
88 #define	PCIE_IS_RP(bus_p) \
89 	((bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) && \
90 	    PCIE_IS_PCIE(bus_p))
91 #define	PCIE_IS_SWU(bus_p) \
92 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_UP)
93 #define	PCIE_IS_SWD(bus_p) \
94 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN)
95 #define	PCIE_IS_SW(bus_p) \
96 	(PCIE_IS_SWU(bus_p) || PCIE_IS_SWD(bus_p))
97 #define	PCIE_IS_BDG(bus_p)  (bus_p->bus_hdr_type == PCI_HEADER_ONE)
98 #define	PCIE_IS_PCI_BDG(bus_p) (PCIE_IS_PCI(bus_p) && PCIE_IS_BDG(bus_p))
99 #define	PCIE_IS_PCIE_BDG(bus_p) \
100 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI)
101 #define	PCIE_IS_PCI2PCIE(bus_p) \
102 	(bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)
103 #define	PCIE_IS_PCIE_SEC(bus_p) \
104 	(PCIE_IS_PCIE(bus_p) && PCIE_IS_BDG(bus_p) && !PCIE_IS_PCIE_BDG(bus_p))
105 #define	PCIX_ECC_VERSION_CHECK(bus_p) \
106 	((bus_p->bus_ecc_ver == PCI_PCIX_VER_1) || \
107 	    (bus_p->bus_ecc_ver == PCI_PCIX_VER_2))
109 #define	PCIE_VENID(bus_p)	(bus_p->bus_dev_ven_id & 0xffff)
110 #define	PCIE_DEVID(bus_p)	((bus_p->bus_dev_ven_id >> 16) & 0xffff)
113 #define	PCIE_GET(sz, bus_p, off) \
114 	pci_config_get ## sz(bus_p->bus_cfg_hdl, off)
115 #define	PCIE_PUT(sz, bus_p, off, val) \
116 	pci_config_put ## sz(bus_p->bus_cfg_hdl, off, val)
117 #define	PCIE_CAP_GET(sz, bus_p, off) \
118 	PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off)
119 #define	PCIE_CAP_PUT(sz, bus_p, off, val) \
120 	PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcie_off, off, \
122 #define	PCIE_AER_GET(sz, bus_p, off) \
123 	PCI_XCAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off)
124 #define	PCIE_AER_PUT(sz, bus_p, off, val) \
125 	PCI_XCAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_aer_off, off, \
127 #define	PCIX_CAP_GET(sz, bus_p, off) \
128 	PCI_CAP_GET ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off)
129 #define	PCIX_CAP_PUT(sz, bus_p, off, val) \
130 	PCI_CAP_PUT ## sz(bus_p->bus_cfg_hdl, NULL, bus_p->bus_pcix_off, off, \
479 #define	PCIE_DBG_CFG(dip, bus_p, name, sz, off, org) \
481 	    ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
482 	    PCIE_GET(sz, bus_p, off))
483 #define	PCIE_DBG_CAP(dip, bus_p, name, sz, off, org) \
485 	    ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
486 	    PCIE_CAP_GET(sz, bus_p, off))
487 #define	PCIE_DBG_AER(dip, bus_p, name, sz, off, org) \
489 	    ddi_get_instance(dip), bus_p->bus_bdf, name, off, org, \
490 	    PCIE_AER_GET(sz, bus_p, off))
582 extern void pf_eh_enter(pcie_bus_t *bus_p);
583 extern void pf_eh_exit(pcie_bus_t *bus_p);