Lines Matching refs:dev
277 yge_dev_t *dev = port->p_dev;
281 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL,
286 val = GMAC_READ_2(dev, pnum, GM_SMI_CTRL);
288 val = GMAC_READ_2(dev, pnum, GM_SMI_DATA);
306 yge_dev_t *dev = port->p_dev;
309 GMAC_WRITE_2(dev, pnum, GM_SMI_DATA, val);
310 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL,
315 if ((GMAC_READ_2(dev, pnum, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0)
352 yge_dev_t *dev = port->p_dev;
363 DEV_LOCK(dev);
368 CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK),
418 GMAC_WRITE_2(dev, port->p_port, GM_GP_CTRL, gpcr);
421 (void) GMAC_READ_2(dev, port->p_port, GM_GP_CTRL);
424 CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac);
428 gpcr = GMAC_READ_2(dev, port->p_port, GM_GP_CTRL);
430 GMAC_WRITE_2(dev, port->p_port, GM_GP_CTRL, gpcr);
433 (void) GMAC_READ_2(dev, port->p_port, GM_GP_CTRL);
436 DEV_UNLOCK(dev);
448 yge_dev_t *dev;
454 dev = port->p_dev;
459 if (dev->d_suspended)
464 GMAC_WRITE_2(dev, pnum, GM_SRC_ADDR_1L + i * 4,
468 GMAC_WRITE_2(dev, pnum, GM_SRC_ADDR_2L + i * 4,
473 mode = GMAC_READ_2(dev, pnum, GM_RX_CTRL);
480 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H1, mchash[0] & 0xffff);
481 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H2, (mchash[0] >> 16) & 0xffff);
482 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H3, mchash[1] & 0xffff);
483 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H4, (mchash[1] >> 16) & 0xffff);
485 GMAC_WRITE_2(dev, pnum, GM_RX_CTRL, mode);
536 yge_setup_rambuffer(yge_dev_t *dev)
542 dev->d_ramsize = CSR_READ_1(dev, B2_E_0) * 4;
543 if (dev->d_ramsize == 0)
546 dev->d_pflags |= PORT_FLAG_RAMBUF;
552 dev->d_rxqsize = (((dev->d_ramsize * 1024 * 2) / 3) & ~(1024 - 1));
553 dev->d_txqsize = (dev->d_ramsize * 1024) - dev->d_rxqsize;
555 for (i = 0, next = 0; i < dev->d_num_port; i++) {
556 dev->d_rxqstart[i] = next;
557 dev->d_rxqend[i] = next + dev->d_rxqsize - 1;
558 next = dev->d_rxqend[i] + 1;
559 dev->d_txqstart[i] = next;
560 dev->d_txqend[i] = next + dev->d_txqsize - 1;
561 next = dev->d_txqend[i] + 1;
566 yge_phy_power(yge_dev_t *dev, boolean_t powerup)
573 CSR_WRITE_1(dev, B0_POWER_CTRL,
576 CSR_WRITE_4(dev, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
579 if (dev->d_hw_id == CHIP_ID_YUKON_XL &&
580 dev->d_hw_rev > CHIP_REV_YU_XL_A1) {
589 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val);
591 val = pci_config_get32(dev->d_pcih, PCI_OUR_REG_1);
593 if (dev->d_hw_id == CHIP_ID_YUKON_XL &&
594 dev->d_hw_rev > CHIP_REV_YU_XL_A1) {
597 if (dev->d_num_port > 1)
602 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val);
604 switch (dev->d_hw_id) {
610 CSR_WRITE_2(dev, B0_CTST, Y2_HW_WOL_OFF);
613 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0);
615 our = pci_config_get32(dev->d_pcih, PCI_OUR_REG_4);
619 pci_config_put32(dev->d_pcih, PCI_OUR_REG_4, our);
622 our = pci_config_get32(dev->d_pcih, PCI_OUR_REG_5);
624 pci_config_put32(dev->d_pcih, PCI_OUR_REG_5, our);
626 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, 0);
629 * Enable workaround for dev 4.107 on Yukon-Ultra
632 our = CSR_READ_4(dev, B2_GP_IO);
634 CSR_WRITE_4(dev, B2_GP_IO, our);
636 (void) CSR_READ_4(dev, B2_GP_IO);
643 for (i = 0; i < dev->d_num_port; i++) {
644 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),
646 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),
650 val = pci_config_get32(dev->d_pcih, PCI_OUR_REG_1);
651 if (dev->d_hw_id == CHIP_ID_YUKON_XL &&
652 dev->d_hw_rev > CHIP_REV_YU_XL_A1) {
654 if (dev->d_num_port > 1)
660 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val);
665 if (dev->d_hw_id == CHIP_ID_YUKON_XL &&
666 dev->d_hw_rev > CHIP_REV_YU_XL_A1) {
674 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val);
675 CSR_WRITE_1(dev, B0_POWER_CTRL,
681 yge_reset(yge_dev_t *dev)
687 ddi_acc_handle_t pcih = dev->d_pcih;
690 if (dev->d_hw_id == CHIP_ID_YUKON_EX) {
691 status = CSR_READ_2(dev, B28_Y2_ASF_STAT_CMD);
697 CSR_WRITE_2(dev, B28_Y2_ASF_STAT_CMD, status);
699 CSR_WRITE_1(dev, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
701 CSR_WRITE_2(dev, B0_CTST, Y2_ASF_DISABLE);
706 CSR_WRITE_1(dev, B0_CTST, CS_RST_SET);
707 CSR_WRITE_1(dev, B0_CTST, CS_RST_CLR);
710 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
714 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
720 CSR_WRITE_1(dev, B0_CTST, CS_MRST_CLR);
722 switch (dev->d_bustype) {
725 CSR_PCI_WRITE_4(dev, Y2_CFG_AER + AER_UNCOR_ERR, 0xffffffff);
728 val = CSR_PCI_READ_4(dev, PEX_UNC_ERR_STAT);
730 dev->d_intrmask &= ~Y2_IS_HW_ERR;
731 dev->d_intrhwemask &= ~Y2_IS_PCI_EXP;
752 yge_phy_power(dev, B_TRUE);
755 for (i = 0; i < dev->d_num_port; i++) {
757 CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
758 CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
760 CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
761 CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
762 if (dev->d_hw_id == CHIP_ID_YUKON_EX ||
763 dev->d_hw_id == CHIP_ID_YUKON_SUPR) {
764 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL),
768 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
771 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
774 CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_ON);
777 CSR_WRITE_4(dev, B2_I2C_IRQ, I2C_CLR_IRQ);
780 CSR_WRITE_1(dev, B2_TI_CTRL, TIM_STOP);
781 CSR_WRITE_1(dev, B2_TI_CTRL, TIM_CLR_IRQ);
784 CSR_WRITE_1(dev, B28_DPT_CTRL, DPT_STOP);
787 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_STOP);
788 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
791 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
794 for (i = 0; i < dev->d_num_port; i++)
795 CSR_WRITE_1(dev, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);
798 for (i = 0; i < dev->d_num_port; i++) {
799 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
801 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), RI_TO_53);
802 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), RI_TO_53);
803 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), RI_TO_53);
804 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), RI_TO_53);
805 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), RI_TO_53);
806 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), RI_TO_53);
807 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), RI_TO_53);
808 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), RI_TO_53);
809 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), RI_TO_53);
810 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), RI_TO_53);
811 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), RI_TO_53);
812 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), RI_TO_53);
816 CSR_WRITE_4(dev, B0_HWE_IMSK, 0);
817 (void) CSR_READ_4(dev, B0_HWE_IMSK);
818 CSR_WRITE_4(dev, B0_IMSK, 0);
819 (void) CSR_READ_4(dev, B0_IMSK);
825 if (dev->d_bustype == PCIX_BUS && dev->d_num_port > 1) {
829 if ((pcix = yge_find_capability(dev, PCI_CAP_ID_PCIX)) != 0) {
833 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
835 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
838 if (dev->d_bustype == PEX_BUS) {
851 yge_error(dev, NULL,
857 CLEARRING(&dev->d_status_ring);
858 SYNCRING(&dev->d_status_ring, DDI_DMA_SYNC_FORDEV);
860 dev->d_stat_cons = 0;
862 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_RST_SET);
863 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_RST_CLR);
866 addr = dev->d_status_ring.r_paddr;
867 CSR_WRITE_4(dev, STAT_LIST_ADDR_LO, YGE_ADDR_LO(addr));
868 CSR_WRITE_4(dev, STAT_LIST_ADDR_HI, YGE_ADDR_HI(addr));
871 CSR_WRITE_2(dev, STAT_LAST_IDX, YGE_STAT_RING_CNT - 1);
872 CSR_WRITE_2(dev, STAT_PUT_IDX, 0);
874 if (dev->d_hw_id == CHIP_ID_YUKON_EC &&
875 dev->d_hw_rev == CHIP_REV_YU_EC_A1) {
876 /* WA for dev. #4.3 */
877 CSR_WRITE_2(dev, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
878 /* WA for dev #4.18 */
879 CSR_WRITE_1(dev, STAT_FIFO_WM, 0x21);
880 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 7);
882 CSR_WRITE_2(dev, STAT_TX_IDX_TH, 10);
883 CSR_WRITE_1(dev, STAT_FIFO_WM, 16);
886 if (dev->d_hw_id == CHIP_ID_YUKON_XL &&
887 dev->d_hw_rev == CHIP_REV_YU_XL_A0)
888 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 4);
890 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 16);
892 CSR_WRITE_4(dev, STAT_ISR_TIMER_INI, 0x0190);
898 CSR_WRITE_4(dev, STAT_TX_TIMER_INI, YGE_USECS(dev, 1000));
901 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_OP_ON);
903 CSR_WRITE_1(dev, STAT_TX_TIMER_CTRL, TIM_START);
904 CSR_WRITE_1(dev, STAT_LEV_TIMER_CTRL, TIM_START);
905 CSR_WRITE_1(dev, STAT_ISR_TIMER_CTRL, TIM_START);
911 yge_dev_t *dev = port->p_dev;
915 port->p_flags = dev->d_pflags;
916 port->p_ppa = ddi_get_instance(dev->d_dip) + (port->p_port * 100);
935 if (dev->d_hw_id == CHIP_ID_YUKON_FE)
947 port->p_mii = mii_alloc(port, dev->d_dip, &yge_mii_ops);
966 CSR_READ_1(dev, B2_MAC_1 + (port->p_port * 8) + i);
976 macp->m_dip = dev->d_dip;
990 yge_add_intr(yge_dev_t *dev, int intr_type)
998 dip = dev->d_dip;
1002 yge_error(dev, NULL,
1014 dev->d_intrcnt = 1;
1016 dev->d_intrsize = count * sizeof (ddi_intr_handle_t);
1017 dev->d_intrh = kmem_zalloc(dev->d_intrsize, KM_SLEEP);
1018 if (dev->d_intrh == NULL) {
1019 yge_error(dev, NULL, "Unable to allocate interrupt handle");
1023 rv = ddi_intr_alloc(dip, dev->d_intrh, intr_type, 0, dev->d_intrcnt,
1026 yge_error(dev, NULL,
1029 kmem_free(dev->d_intrh, dev->d_intrsize);
1033 if ((rv = ddi_intr_get_pri(dev->d_intrh[0], &dev->d_intrpri)) !=
1035 for (i = 0; i < dev->d_intrcnt; i++)
1036 (void) ddi_intr_free(dev->d_intrh[i]);
1037 yge_error(dev, NULL,
1039 kmem_free(dev->d_intrh, dev->d_intrsize);
1043 if ((rv = ddi_intr_get_cap(dev->d_intrh[0], &dev->d_intrcap)) !=
1045 yge_error(dev, NULL,
1047 for (i = 0; i < dev->d_intrcnt; i++)
1048 (void) ddi_intr_free(dev->d_intrh[i]);
1049 kmem_free(dev->d_intrh, dev->d_intrsize);
1054 for (i = 0; i < dev->d_intrcnt; i++) {
1055 if ((rv = ddi_intr_add_handler(dev->d_intrh[i], yge_intr,
1056 dev, NULL)) != DDI_SUCCESS) {
1057 yge_error(dev, NULL,
1060 (void) ddi_intr_remove_handler(dev->d_intrh[j]);
1061 for (i = 0; i < dev->d_intrcnt; i++)
1062 (void) ddi_intr_free(dev->d_intrh[i]);
1063 kmem_free(dev->d_intrh, dev->d_intrsize);
1068 mutex_init(&dev->d_rxlock, NULL, MUTEX_DRIVER,
1069 DDI_INTR_PRI(dev->d_intrpri));
1070 mutex_init(&dev->d_txlock, NULL, MUTEX_DRIVER,
1071 DDI_INTR_PRI(dev->d_intrpri));
1072 mutex_init(&dev->d_phylock, NULL, MUTEX_DRIVER,
1073 DDI_INTR_PRI(dev->d_intrpri));
1074 mutex_init(&dev->d_task_mtx, NULL, MUTEX_DRIVER,
1075 DDI_INTR_PRI(dev->d_intrpri));
1081 yge_attach_intr(yge_dev_t *dev)
1083 dev_info_t *dip = dev->d_dip;
1090 yge_error(dev, NULL,
1108 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_MSIX)) ==
1114 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_MSI)) ==
1120 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_FIXED)) ==
1125 yge_error(dev, NULL, "Unable to configure any interrupts");
1130 yge_intr_enable(yge_dev_t *dev)
1133 if (dev->d_intrcap & DDI_INTR_FLAG_BLOCK) {
1135 (void) ddi_intr_block_enable(dev->d_intrh, dev->d_intrcnt);
1138 for (i = 0; i < dev->d_intrcnt; i++)
1139 (void) ddi_intr_enable(dev->d_intrh[i]);
1144 yge_intr_disable(yge_dev_t *dev)
1148 if (dev->d_intrcap & DDI_INTR_FLAG_BLOCK) {
1149 (void) ddi_intr_block_disable(dev->d_intrh, dev->d_intrcnt);
1151 for (i = 0; i < dev->d_intrcnt; i++)
1152 (void) ddi_intr_disable(dev->d_intrh[i]);
1157 yge_find_capability(yge_dev_t *dev, uint8_t cap)
1161 ddi_acc_handle_t pcih = dev->d_pcih;
1179 yge_attach(yge_dev_t *dev)
1181 dev_info_t *dip = dev->d_dip;
1186 if (pci_config_setup(dip, &dev->d_pcih) != DDI_SUCCESS) {
1187 yge_error(dev, NULL, "Unable to map PCI configuration space");
1196 pm_cap = yge_find_capability(dev, PCI_CAP_ID_PM);
1199 pmcsr = pci_config_get16(dev->d_pcih, pm_cap + PCI_PMCSR);
1201 pci_config_put16(dev->d_pcih, pm_cap + PCI_PMCSR,
1206 pci_config_put16(dev->d_pcih, PCI_CONF_COMM,
1207 pci_config_get16(dev->d_pcih, PCI_CONF_COMM) |
1212 rv = ddi_regs_map_setup(dip, 1, &dev->d_regs, 0, 0, &yge_regs_attr,
1213 &dev->d_regsh);
1215 yge_error(dev, NULL, "Unable to map device registers");
1221 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1222 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0);
1223 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1225 CSR_WRITE_2(dev, B0_CTST, CS_RST_CLR);
1226 dev->d_hw_id = CSR_READ_1(dev, B2_CHIP_ID);
1227 dev->d_hw_rev = (CSR_READ_1(dev, B2_MAC_CFG) >> 4) & 0x0f;
1236 if (dev->d_hw_id < CHIP_ID_YUKON_XL ||
1237 dev->d_hw_id >= CHIP_ID_YUKON_UL_2) {
1238 yge_error(dev, NULL, "Unknown device: id=0x%02x, rev=0x%02x",
1239 dev->d_hw_id, dev->d_hw_rev);
1246 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET);
1247 CSR_WRITE_2(dev, B0_CTST, CS_RST_CLR);
1248 dev->d_pmd = CSR_READ_1(dev, B2_PMD_TYP);
1249 if (dev->d_pmd == 'L' || dev->d_pmd == 'S' || dev->d_pmd == 'P')
1250 dev->d_coppertype = 0;
1252 dev->d_coppertype = 1;
1254 dev->d_num_port = 1;
1255 if ((CSR_READ_1(dev, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1257 if (!(CSR_READ_1(dev, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1258 dev->d_num_port++;
1262 if (yge_find_capability(dev, PCI_CAP_ID_PCI_E) != 0) {
1263 dev->d_bustype = PEX_BUS;
1264 } else if (yge_find_capability(dev, PCI_CAP_ID_PCIX) != 0) {
1265 dev->d_bustype = PCIX_BUS;
1267 dev->d_bustype = PCI_BUS;
1270 switch (dev->d_hw_id) {
1272 dev->d_clock = 125; /* 125 Mhz */
1275 dev->d_clock = 125; /* 125 Mhz */
1278 dev->d_clock = 125; /* 125 Mhz */
1281 dev->d_clock = 125; /* 125 Mhz */
1284 dev->d_clock = 125; /* 125 Mhz */
1287 dev->d_clock = 100; /* 100 Mhz */
1290 dev->d_clock = 50; /* 50 Mhz */
1293 dev->d_clock = 156; /* 156 Mhz */
1296 dev->d_clock = 156; /* 156 Mhz */
1300 dev->d_process_limit = YGE_RX_RING_CNT/2;
1302 rv = yge_alloc_ring(NULL, dev, &dev->d_status_ring, YGE_STAT_RING_CNT);
1307 dev->d_task_q = ddi_taskq_create(dip, "tq", 1, TASKQ_DEFAULTPRI, 0);
1308 if (dev->d_task_q == NULL) {
1309 yge_error(dev, NULL, "failed to create taskq");
1314 cv_init(&dev->d_task_cv, NULL, CV_DRIVER, NULL);
1317 if ((rv = yge_attach_intr(dev)) != DDI_SUCCESS) {
1322 dev->d_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1323 dev->d_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1327 yge_reset(dev);
1329 yge_setup_rambuffer(dev);
1332 for (int i = 0; i < dev->d_num_port; i++) {
1333 yge_port_t *port = dev->d_port[i];
1339 yge_intr_enable(dev);
1342 dev->d_periodic = ddi_periodic_add(yge_tick, dev, 1000000000, 0);
1344 for (int i = 0; i < dev->d_num_port; i++) {
1345 yge_port_t *port = dev->d_port[i];
1356 if (ddi_taskq_dispatch(dev->d_task_q, yge_task, dev, DDI_SLEEP) !=
1358 yge_error(dev, NULL, "failed to start taskq");
1367 yge_detach(dev);
1408 yge_detach(yge_dev_t *dev)
1413 if (dev->d_periodic)
1414 ddi_periodic_delete(dev->d_periodic);
1416 for (int i = 0; i < dev->d_num_port; i++) {
1417 yge_uninit_port(dev->d_port[i]);
1423 CSR_WRITE_4(dev, B0_IMSK, 0);
1424 (void) CSR_READ_4(dev, B0_IMSK);
1425 CSR_WRITE_4(dev, B0_HWE_IMSK, 0);
1426 (void) CSR_READ_4(dev, B0_HWE_IMSK);
1429 CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_OFF);
1432 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET);
1434 yge_free_ring(&dev->d_status_ring);
1436 if (dev->d_task_q != NULL) {
1437 yge_dispatch(dev, YGE_TASK_EXIT);
1438 ddi_taskq_destroy(dev->d_task_q);
1439 dev->d_task_q = NULL;
1442 cv_destroy(&dev->d_task_cv);
1444 yge_intr_disable(dev);
1446 if (dev->d_intrh != NULL) {
1447 for (int i = 0; i < dev->d_intrcnt; i++) {
1448 (void) ddi_intr_remove_handler(dev->d_intrh[i]);
1449 (void) ddi_intr_free(dev->d_intrh[i]);
1451 kmem_free(dev->d_intrh, dev->d_intrsize);
1452 mutex_destroy(&dev->d_phylock);
1453 mutex_destroy(&dev->d_txlock);
1454 mutex_destroy(&dev->d_rxlock);
1455 mutex_destroy(&dev->d_task_mtx);
1457 if (dev->d_regsh != NULL)
1458 ddi_regs_map_free(&dev->d_regsh);
1460 if (dev->d_pcih != NULL)
1461 pci_config_teardown(&dev->d_pcih);
1465 yge_alloc_ring(yge_port_t *port, yge_dev_t *dev, yge_ring_t *ring, uint32_t num)
1474 if (port && !dev)
1475 dev = port->p_dev;
1476 dip = dev->d_dip;
1483 yge_error(dev, port, "Unable to allocate ring DMA handle");
1491 yge_error(dev, port, "Unable to allocate ring DMA memory");
1503 yge_error(dev, port, "Unable to bind ring DMA handle");
1530 yge_dev_t *dev = port->p_dev;
1540 rv = ddi_dma_alloc_handle(dev->d_dip, &yge_buf_dma_attr,
1708 yge_suspend(yge_dev_t *dev)
1710 for (int i = 0; i < dev->d_num_port; i++) {
1711 yge_port_t *port = dev->d_port[i];
1716 DEV_LOCK(dev);
1718 for (int i = 0; i < dev->d_num_port; i++) {
1719 yge_port_t *port = dev->d_port[i];
1727 CSR_WRITE_4(dev, B0_IMSK, 0);
1728 (void) CSR_READ_4(dev, B0_IMSK);
1729 CSR_WRITE_4(dev, B0_HWE_IMSK, 0);
1730 (void) CSR_READ_4(dev, B0_HWE_IMSK);
1732 yge_phy_power(dev, B_FALSE);
1735 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET);
1736 dev->d_suspended = B_TRUE;
1738 DEV_UNLOCK(dev);
1744 yge_resume(yge_dev_t *dev)
1748 DEV_LOCK(dev);
1751 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1753 if ((pm_cap = yge_find_capability(dev, PCI_CAP_ID_PM)) != 0) {
1755 pmcsr = pci_config_get16(dev->d_pcih, pm_cap + PCI_PMCSR);
1757 pci_config_put16(dev->d_pcih, pm_cap + PCI_PMCSR,
1762 pci_config_put16(dev->d_pcih, PCI_CONF_COMM,
1763 pci_config_get16(dev->d_pcih, PCI_CONF_COMM) |
1767 switch (dev->d_hw_id) {
1771 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0);
1775 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1777 yge_reset(dev);
1780 CSR_WRITE_4(dev, B0_IMSK, 0);
1781 CSR_WRITE_4(dev, B0_IMSK, Y2_IS_HW_ERR | Y2_IS_STAT_BMU);
1782 CSR_WRITE_4(dev, B0_HWE_IMSK,
1786 for (int i = 0; i < dev->d_num_port; i++) {
1787 yge_port_t *port = dev->d_port[i];
1793 dev->d_suspended = B_FALSE;
1795 DEV_UNLOCK(dev);
1798 for (int i = 0; i < dev->d_num_port; i++) {
1799 yge_port_t *port = dev->d_port[i];
1813 yge_dev_t *dev = port->p_dev;
1819 ASSERT(mutex_owned(&dev->d_rxlock));
1831 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) &&
1832 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) {
1865 CSR_WRITE_2(dev,
1924 yge_restart_task(yge_dev_t *dev)
1928 DEV_LOCK(dev);
1931 for (int i = 0; i < dev->d_num_port; i++) {
1932 port = dev->d_port[i];
1934 yge_stop_port(dev->d_port[i]);
1936 yge_reset(dev);
1937 for (int i = 0; i < dev->d_num_port; i++) {
1938 port = dev->d_port[i];
1944 DEV_UNLOCK(dev);
1946 for (int i = 0; i < dev->d_num_port; i++) {
1947 port = dev->d_port[i];
1958 yge_dev_t *dev = arg;
1964 DEV_LOCK(dev);
1966 if (dev->d_suspended) {
1967 DEV_UNLOCK(dev);
1971 for (int i = 0; i < dev->d_num_port; i++) {
1972 port = dev->d_port[i];
1986 idx = CSR_READ_2(dev, ridx);
2004 DEV_UNLOCK(dev);
2006 yge_dispatch(dev, YGE_TASK_RESTART);
2009 for (int i = 0; i < dev->d_num_port; i++) {
2010 port = dev->d_port[i];
2022 yge_dev_t *dev = port->p_dev;
2027 status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));
2031 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2037 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2055 yge_dev_t *dev = port->p_dev;
2060 CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL),
2066 CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL),
2072 CSR_WRITE_4(dev, MR_ADDR(port->p_port, TX_GMF_CTRL_T),
2078 CSR_WRITE_4(dev, Q_ADDR(port->p_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
2083 CSR_WRITE_4(dev, Q_ADDR(port->p_txq, Q_CSR), BMU_CLR_IRQ_TCP);
2088 yge_intr_hwerr(yge_dev_t *dev)
2093 status = CSR_READ_4(dev, B0_HWE_ISRC);
2096 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2105 yge_error(dev, NULL, "PCI Express protocol violation error");
2112 yge_error(dev, NULL, "Unexpected IRQ Status error");
2114 yge_error(dev, NULL, "Unexpected IRQ Master error");
2116 v16 = pci_config_get16(dev->d_pcih, PCI_CONF_STAT);
2117 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2118 pci_config_put16(dev->d_pcih, PCI_CONF_STAT, v16 |
2121 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2136 v32 = CSR_PCI_READ_4(dev, PEX_UNC_ERR_STAT);
2139 yge_error(dev, NULL,
2147 tlphead[i] = CSR_PCI_READ_4(dev,
2151 dev->d_intrhwemask &= ~Y2_IS_PCI_EXP;
2152 CSR_WRITE_4(dev, B0_HWE_IMSK,
2153 dev->d_intrhwemask);
2154 (void) CSR_READ_4(dev, B0_HWE_IMSK);
2158 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2159 CSR_PCI_WRITE_4(dev, PEX_UNC_ERR_STAT, 0xffffffff);
2160 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2163 if ((status & Y2_HWE_L1_MASK) != 0 && dev->d_port[YGE_PORT_A] != NULL)
2164 yge_handle_hwerr(dev->d_port[YGE_PORT_A], status);
2165 if ((status & Y2_HWE_L2_MASK) != 0 && dev->d_port[YGE_PORT_B] != NULL)
2166 yge_handle_hwerr(dev->d_port[YGE_PORT_B], status >> 8);
2173 yge_handle_events(yge_dev_t *dev, mblk_t **heads, mblk_t **tails, int *txindex)
2184 idx = CSR_READ_2(dev, STAT_PUT_IDX);
2185 if (idx == dev->d_stat_cons) {
2189 ring = &dev->d_status_ring;
2191 for (cons = dev->d_stat_cons; cons != idx; ) {
2196 yge_error(dev, NULL, "Status descriptor error: "
2206 port = dev->d_port[pnum];
2208 yge_error(dev, NULL, "Invalid port opcode: 0x%08x",
2234 yge_error(dev, NULL, "Unhandled opcode: 0x%08x",
2245 if (rxprogs[pnum] > dev->d_process_limit) {
2250 dev->d_stat_cons = cons;
2251 if (dev->d_stat_cons != CSR_READ_2(dev, STAT_PUT_IDX))
2261 yge_dev_t *dev;
2269 dev = (void *)arg1;
2276 port1 = dev->d_port[YGE_PORT_A];
2277 port2 = dev->d_port[YGE_PORT_B];
2279 RX_LOCK(dev);
2281 if (dev->d_suspended) {
2282 RX_UNLOCK(dev);
2287 status = CSR_READ_4(dev, B0_Y2_SP_ISRC2);
2289 (status & dev->d_intrmask) == 0) { /* Stray interrupt ? */
2291 CSR_WRITE_4(dev, B0_Y2_SP_ICR, 2);
2292 RX_UNLOCK(dev);
2297 yge_intr_hwerr(dev);
2310 dev->d_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
2311 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask);
2312 (void) CSR_READ_4(dev, B0_IMSK);
2317 dev->d_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
2318 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask);
2319 (void) CSR_READ_4(dev, B0_IMSK);
2323 while (yge_handle_events(dev, heads, tails, txindex))
2328 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_CLR_IRQ);
2332 CSR_WRITE_4(dev, B0_Y2_SP_ICR, 2);
2334 RX_UNLOCK(dev);
2337 yge_dispatch(dev, dispatch_wrk);
2378 yge_dev_t *dev = port->p_dev;
2381 switch (dev->d_hw_id) {
2383 if (dev->d_hw_rev == CHIP_REV_YU_EX_A0)
2387 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
2390 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
2397 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_AE_THR),
2400 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
2404 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
2414 yge_dev_t *dev = port->p_dev;
2438 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_SET);
2439 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_CLR);
2440 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_F_LOOPB_OFF);
2441 if (dev->d_hw_id == CHIP_ID_YUKON_EX)
2442 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL),
2449 GMAC_WRITE_2(dev, pnum, GM_GP_CTRL, 0);
2452 (void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));
2458 GMAC_WRITE_2(dev, pnum, GM_RX_CTRL, GM_RXCR_CRC_DIS);
2461 GMAC_WRITE_2(dev, pnum, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2464 GMAC_WRITE_2(dev, pnum, GM_TX_FLOW_CTRL, 0xffff);
2467 GMAC_WRITE_2(dev, pnum, GM_TX_PARAM,
2476 GMAC_WRITE_2(dev, pnum, GM_SERIAL_MODE, gmac);
2479 GMAC_WRITE_2(dev, pnum, GM_TX_IRQ_MSK, 0);
2480 GMAC_WRITE_2(dev, pnum, GM_RX_IRQ_MSK, 0);
2481 GMAC_WRITE_2(dev, pnum, GM_TR_IRQ_MSK, 0);
2484 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);
2485 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_CLR);
2487 if (dev->d_hw_id == CHIP_ID_YUKON_FE_P ||
2488 dev->d_hw_id == CHIP_ID_YUKON_EX)
2490 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg);
2496 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
2504 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) &&
2505 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0))
2508 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg);
2511 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);
2512 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_CLR);
2513 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_OPER_ON);
2516 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
2517 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
2521 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) &&
2522 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) {
2523 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),
2525 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),
2528 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),
2530 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),
2537 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) &&
2538 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) {
2540 reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA));
2542 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg);
2549 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL),
2552 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_ENA_ARB);
2558 CSR_WRITE_1(dev, RB_ADDR(port->p_txsq, RB_CTRL), RB_RST_SET);
2561 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_CLR_RESET);
2562 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_OPER_INIT);
2563 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_FIFO_OP_ON);
2564 CSR_WRITE_2(dev, Q_ADDR(txq, Q_WM), MSK_BMU_TX_WM);
2566 switch (dev->d_hw_id) {
2568 if (dev->d_hw_rev == CHIP_REV_YU_EC_U_A0) {
2570 CSR_WRITE_2(dev, Q_ADDR(txq, Q_AL), MSK_ECU_TXFF_LEV);
2578 if (dev->d_hw_rev == CHIP_REV_YU_EX_B0)
2579 CSR_WRITE_4(dev, Q_ADDR(txq, Q_F), F_TX_CHK_AUTO_OFF);
2584 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_CLR_RESET);
2585 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_OPER_INIT);
2586 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_FIFO_OP_ON);
2587 if (dev->d_bustype == PEX_BUS) {
2588 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), 0x80);
2590 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), MSK_BMU_RX_WM);
2592 if (dev->d_hw_id == CHIP_ID_YUKON_EC_U &&
2593 dev->d_hw_rev >= CHIP_REV_YU_EC_U_A1) {
2595 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
2601 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR),
2607 if (port == dev->d_port[YGE_PORT_A]) {
2608 dev->d_intrmask |= Y2_IS_PORT_A;
2609 dev->d_intrhwemask |= Y2_HWE_L1_MASK;
2610 } else if (port == dev->d_port[YGE_PORT_B]) {
2611 dev->d_intrmask |= Y2_IS_PORT_B;
2612 dev->d_intrhwemask |= Y2_HWE_L2_MASK;
2614 CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask);
2615 (void) CSR_READ_4(dev, B0_HWE_IMSK);
2616 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask);
2617 (void) CSR_READ_4(dev, B0_IMSK);
2620 gmac = GMAC_READ_2(dev, pnum, GM_GP_CTRL);
2624 (void) GMAC_READ_2(dev, pnum, GM_GP_CTRL);
2633 yge_dev_t *dev;
2639 dev = port->p_dev;
2648 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_CLR);
2649 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_START), dev->d_rxqstart[pnum] / 8);
2650 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_END), dev->d_rxqend[pnum] / 8);
2651 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_WP), dev->d_rxqstart[pnum] / 8);
2652 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RP), dev->d_rxqstart[pnum] / 8);
2655 (dev->d_rxqend[pnum] + 1 - dev->d_rxqstart[pnum] - RB_ULPP) / 8;
2657 (dev->d_rxqend[pnum] + 1 - dev->d_rxqstart[pnum] - RB_LLPP_B) / 8;
2659 if (dev->d_rxqsize < MSK_MIN_RXQ_SIZE)
2662 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_UTPP), utpp);
2663 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_LTPP), ltpp);
2666 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_ENA_OP_MD);
2667 (void) CSR_READ_1(dev, RB_ADDR(rxq, RB_CTRL));
2670 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_CLR);
2671 CSR_WRITE_4(dev, RB_ADDR(txq, RB_START), dev->d_txqstart[pnum] / 8);
2672 CSR_WRITE_4(dev, RB_ADDR(txq, RB_END), dev->d_txqend[pnum] / 8);
2673 CSR_WRITE_4(dev, RB_ADDR(txq, RB_WP), dev->d_txqstart[pnum] / 8);
2674 CSR_WRITE_4(dev, RB_ADDR(txq, RB_RP), dev->d_txqstart[pnum] / 8);
2676 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_STFWD);
2677 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_OP_MD);
2678 (void) CSR_READ_1(dev, RB_ADDR(txq, RB_CTRL));
2682 yge_set_prefetch(yge_dev_t *dev, int qaddr, yge_ring_t *ring)
2685 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
2687 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
2690 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
2692 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
2695 CSR_WRITE_2(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
2698 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
2701 (void) CSR_READ_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
2707 yge_dev_t *dev = port->p_dev;
2714 dev = port->p_dev;
2723 dev->d_intrmask &= ~Y2_IS_PORT_A;
2724 dev->d_intrhwemask &= ~Y2_HWE_L1_MASK;
2726 dev->d_intrmask &= ~Y2_IS_PORT_B;
2727 dev->d_intrhwemask &= ~Y2_HWE_L2_MASK;
2729 CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask);
2730 (void) CSR_READ_4(dev, B0_HWE_IMSK);
2731 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask);
2732 (void) CSR_READ_4(dev, B0_IMSK);
2735 val = GMAC_READ_2(dev, pnum, GM_GP_CTRL);
2737 GMAC_WRITE_2(dev, pnum, GM_GP_CTRL, val);
2739 (void) GMAC_READ_2(dev, pnum, GM_GP_CTRL);
2745 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP);
2746 val = CSR_READ_4(dev, Q_ADDR(txq, Q_CSR));
2749 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP);
2750 val = CSR_READ_4(dev, Q_ADDR(txq, Q_CSR));
2759 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET | RB_DIS_OP_MD);
2762 CSR_WRITE_1(dev, MR_ADDR(pnum, GMAC_IRQ_MSK), 0);
2765 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_DIS_ARB);
2768 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
2771 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(txq, PREF_UNIT_CTRL_REG),
2775 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET);
2778 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);
2780 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_PAUSE_OFF);
2794 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
2796 if (CSR_READ_1(dev, RB_ADDR(rxq, Q_RSL)) ==
2797 CSR_READ_1(dev, RB_ADDR(rxq, Q_RL)))
2805 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
2807 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(rxq, PREF_UNIT_CTRL_REG),
2810 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
2812 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);
2821 GMAC_READ_4(dev, x, y)
2830 yge_dev_t *dev;
2835 dev = port->p_dev;
2838 gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR);
2839 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
2845 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac);
2851 yge_dev_t *dev;
2856 dev = port->p_dev;
2859 if (dev->d_suspended || !port->p_running) {
2864 gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR);
2865 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
2913 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac);
3088 yge_dev_t *dev = port->p_dev;
3090 DEV_LOCK(dev);
3091 if (!dev->d_suspended)
3098 DEV_UNLOCK(dev);
3369 yge_dispatch(yge_dev_t *dev, int flag)
3371 TASK_LOCK(dev);
3372 dev->d_task_flags |= flag;
3373 TASK_SIGNAL(dev);
3374 TASK_UNLOCK(dev);
3380 yge_dev_t *dev = arg;
3385 TASK_LOCK(dev);
3386 while ((flags = dev->d_task_flags) == 0)
3387 TASK_WAIT(dev);
3389 dev->d_task_flags = 0;
3390 TASK_UNLOCK(dev);
3402 yge_restart_task(dev);
3407 yge_error(yge_dev_t *dev, yge_port_t *port, char *fmt, ...)
3417 if (dev == NULL && port == NULL) {
3423 ppa = ddi_get_instance(dev->d_dip);
3431 yge_dev_t *dev;
3436 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP);
3437 dev->d_port[0] = kmem_zalloc(sizeof (yge_port_t), KM_SLEEP);
3438 dev->d_port[1] = kmem_zalloc(sizeof (yge_port_t), KM_SLEEP);
3439 dev->d_dip = dip;
3440 ddi_set_driver_private(dip, dev);
3442 dev->d_port[0]->p_port = 0;
3443 dev->d_port[0]->p_dev = dev;
3444 dev->d_port[1]->p_port = 0;
3445 dev->d_port[1]->p_dev = dev;
3447 rv = yge_attach(dev);
3450 kmem_free(dev->d_port[1], sizeof (yge_port_t));
3451 kmem_free(dev->d_port[0], sizeof (yge_port_t));
3452 kmem_free(dev, sizeof (*dev));
3457 dev = ddi_get_driver_private(dip);
3458 ASSERT(dev != NULL);
3459 return (yge_resume(dev));
3469 yge_dev_t *dev;
3475 dev = ddi_get_driver_private(dip);
3478 for (int i = 0; i < dev->d_num_port; i++) {
3480 if (((mh = dev->d_port[i]->p_mh) != NULL) &&
3491 ASSERT(dip == dev->d_dip);
3492 yge_detach(dev);
3494 for (int i = 0; i < dev->d_num_port; i++) {
3495 if ((mh = dev->d_port[i]->p_mh) != NULL) {
3500 kmem_free(dev->d_port[1], sizeof (yge_port_t));
3501 kmem_free(dev->d_port[0], sizeof (yge_port_t));
3502 kmem_free(dev, sizeof (*dev));
3506 dev = ddi_get_driver_private(dip);
3507 ASSERT(dev != NULL);
3508 return (yge_suspend(dev));
3518 yge_dev_t *dev;
3520 dev = ddi_get_driver_private(dip);
3521 ASSERT(dev != NULL);
3524 for (int i = 0; i < dev->d_num_port; i++) {
3525 yge_port_t *port = dev->d_port[i];
3531 CSR_WRITE_4(dev, B0_IMSK, 0);
3532 (void) CSR_READ_4(dev, B0_IMSK);
3533 CSR_WRITE_4(dev, B0_HWE_IMSK, 0);
3534 (void) CSR_READ_4(dev, B0_HWE_IMSK);
3537 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET);