Cross Reference: /illumos-gate/usr/src/uts/common/io/yge/yge.c

Lines Matching refs:MR_ADDR
368 		CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK),
424 		CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac);
644 			CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),
646 			CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),
757 		CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
758 		CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
760 		CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
761 		CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
764 			CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL),
768 		CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
795 		CSR_WRITE_1(dev, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);
2027 	status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));
2031 		CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2037 		CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2072 		CSR_WRITE_4(dev, MR_ADDR(port->p_port, TX_GMF_CTRL_T),
2387 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
2390 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
2397 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_AE_THR),
2400 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
2404 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
2438 	CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_SET);
2439 	CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_CLR);
2440 	CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_F_LOOPB_OFF);
2442 		CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL),
2452 	(void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));
2484 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);
2485 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_CLR);
2490 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg);
2496 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
2508 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg);
2511 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);
2512 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_CLR);
2513 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_OPER_ON);
2516 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
2517 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
2523 			CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),
2525 			CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),
2528 			CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),
2530 			CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),
2540 		reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA));
2542 		CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg);
2549 	CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL),
2552 	CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_ENA_ARB);
2762 	CSR_WRITE_1(dev, MR_ADDR(pnum, GMAC_IRQ_MSK), 0);
2765 	CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_DIS_ARB);
2778 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);
2780 	CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_PAUSE_OFF);
2812 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);