Lines Matching defs:status
88 xge_hal_status_e status;
91 status = xge_hal_mgmt_reg_read(devh, 0, offset, &retval);
92 if (status != XGE_HAL_OK) {
93 return status;
128 xge_hal_status_e status;
131 status = xge_hal_mgmt_reg_read(devh, 1, offset, &retval);
132 if (status != XGE_HAL_OK)
133 return status;
163 xge_hal_status_e status;
165 status = xge_hal_mgmt_reg_write(devh, 0, offset, value);
166 if (status != XGE_HAL_OK) {
167 return status;
193 xge_hal_status_e status;
197 status = xge_hal_mgmt_about(devh, &about_info,
199 if (status != XGE_HAL_OK) {
200 return status;
249 xge_hal_status_e status;
257 status = xge_hal_mgmt_hw_stats(devh, &hw,
259 if (status != XGE_HAL_OK) {
260 return status;
290 status = xge_hal_mgmt_pcim_stats(devh, &pcim,
292 if (status != XGE_HAL_OK) {
293 return status;
390 xge_hal_status_e status;
398 status = xge_hal_mgmt_hw_stats(devh, &hw,
400 if (status != XGE_HAL_OK) {
401 return status;
510 status = xge_hal_mgmt_pcim_stats(devh, &pcim,
512 if (status != XGE_HAL_OK) {
513 return status;
691 xge_hal_status_e status;
705 status = xge_hal_mgmt_hw_stats(devh, &hw,
707 if (status != XGE_HAL_OK) {
708 return status;
817 xge_hal_status_e status;
831 status = xge_hal_mgmt_hw_stats(devh, &hw,
833 if (status != XGE_HAL_OK) {
834 return status;
884 xge_hal_status_e status;
893 status = xge_hal_mgmt_device_stats(hldev, &devstat,
895 if (status != XGE_HAL_OK) {
896 return status;
953 status = xge_hal_mgmt_channel_stats(channel, &chstat,
955 if (status != XGE_HAL_OK) {
956 return status;
992 status = xge_hal_mgmt_channel_stats(channel, &chstat,
994 if (status != XGE_HAL_OK) {
995 return status;
1086 xge_hal_status_e status;
1093 status = xge_hal_mgmt_sw_stats(hldev, &sw_dev_err_stats,
1095 if (status != XGE_HAL_OK) {
1096 return status;
1169 xge_hal_status_e status;
1175 status = xge_hal_mgmt_pci_config(devh, &pci_config,
1177 if (status != XGE_HAL_OK) {
1178 return status;
1184 __HAL_AUX_ENTRY("status", pci_config.status, "0x%04X");
1402 xge_hal_status_e status;
1411 status = xge_hal_aux_about_read(hldev, XGE_HAL_DUMP_BUF_SIZE,
1414 if (status != XGE_HAL_OK) {
1422 status = xge_hal_mgmt_reg_read(hldev, 0, offset*8, &retval);
1423 if (status != XGE_HAL_OK) {
1434 status = xge_hal_aux_pci_config_read(hldev, XGE_HAL_DUMP_BUF_SIZE,
1437 if (status != XGE_HAL_OK) {
1442 status = xge_hal_aux_stats_tmac_read(hldev, XGE_HAL_DUMP_BUF_SIZE,
1445 if (status != XGE_HAL_OK) {
1450 status = xge_hal_aux_stats_rmac_read(hldev, XGE_HAL_DUMP_BUF_SIZE,
1453 if (status != XGE_HAL_OK) {
1458 status = xge_hal_aux_stats_pci_read(hldev, XGE_HAL_DUMP_BUF_SIZE,
1461 if (status != XGE_HAL_OK) {
1467 status = xge_hal_aux_stats_herc_enchanced(hldev,
1469 if (status != XGE_HAL_OK) {
1475 status = xge_hal_aux_stats_sw_dev_read(hldev, XGE_HAL_DUMP_BUF_SIZE,
1477 if (status != XGE_HAL_OK) {
1482 status = xge_hal_aux_channel_read(hldev, XGE_HAL_DUMP_BUF_SIZE,
1485 if (status != XGE_HAL_OK) {
1490 status = xge_hal_aux_stats_hal_read(hldev, XGE_HAL_DUMP_BUF_SIZE,
1493 if (status != XGE_HAL_OK) {
1501 return status;
1521 xge_hal_status_e status;
1525 status = xge_hal_mgmt_driver_config(&drv_config,
1527 if (status != XGE_HAL_OK) {
1528 return status;
1559 xge_hal_status_e status;
1580 status = xge_hal_mgmt_device_config(devh, dev_config,
1582 if (status != XGE_HAL_OK) {
1585 return status;