Lines Matching defs:rti
911 xge_hal_rti_config_t *rti;
915 rti = &hldev->config.ring.queue[i].rti;
930 rti->urange_a = 10;
931 rti->urange_b = 20;
932 rti->urange_c = 30;
933 rti->ufc_a = 1; /* <= for netpipe type of tests */
934 rti->ufc_b = 4;
935 rti->ufc_c = 4;
936 rti->ufc_d = 4; /* <= 99% of a bandwidth traffic counts here */
937 rti->timer_ac_en = 1;
938 rti->timer_val_us = 5; /* for optimal bus efficiency usage */
1120 xge_hal_rti_config_t *rti = &hldev->config.ring.queue[i].rti;
1125 if (rti->timer_val_us) {
1130 rti->timer_val_us / 8;
1135 rx_interval = rti->timer_val_us;
1138 if (rti->timer_ac_en) {
1144 if (rti->urange_a ||
1145 rti->urange_b ||
1146 rti->urange_c ||
1147 rti->ufc_a ||
1148 rti->ufc_b ||
1149 rti->ufc_c ||
1150 rti->ufc_d) {
1151 data1 |=XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(rti->urange_a) |
1152 XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(rti->urange_b) |
1153 XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(rti->urange_c);
1155 data2 |= XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(rti->ufc_a) |
1156 XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(rti->ufc_b) |
1157 XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(rti->ufc_c) |
1158 XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(rti->ufc_d);
3426 ufc = hldev->config.ring.queue[ring_no].rti.ufc_a;
3435 hldev->config.ring.queue[i].rti.ufc_a = ufc;
3445 hldev->config.ring.queue[i].rti.ufc_a = ufc;
3654 if (hldev->config.ring.queue[i].rti.urange_a)
6459 channel->rti = (u8)ring_qid;