Cross Reference: /illumos-gate/usr/src/uts/common/io/xge/drv/xgell.c

Lines Matching refs:dtr
192  * To replenish all freed dtr(s) with buffers in free pool. It's called by
200 	xge_hal_dtr_h dtr;
207 	    (xge_hal_ring_dtr_reserve(ring->channelh, &dtr) == XGE_HAL_OK)) {
218 		    xge_hal_ring_dtr_private(ring->channelh, dtr);
219 		xge_hal_ring_dtr_1b_set(dtr, rx_buffer->dma_addr,
223 		xge_hal_ring_dtr_post(ring->channelh, dtr);
528  * The dtr should be post right away.
531 xgell_rx_dtr_replenish(xge_hal_channel_h channelh, xge_hal_dtr_h dtr, int index,
552 	rxd_priv = (xgell_rxd_priv_t *)xge_hal_ring_dtr_private(channelh, dtr);
553 	xge_hal_ring_dtr_1b_set(dtr, rx_buffer->dma_addr, bf_pool->size);
703 xgell_rx_1b_callback(xge_hal_channel_h channelh, xge_hal_dtr_h dtr, u8 t_code,
723 		    xge_hal_ring_dtr_private(channelh, dtr));
728 		xge_hal_ring_dtr_1b_get(channelh, dtr, &dma_data, &pkt_length);
729 		xge_hal_ring_dtr_info_get(channelh, dtr, &ext_info);
734 			xge_debug_ll(XGE_ERR, "%s%d: rx: dtr 0x%"PRIx64
736 			    lldev->instance, (uint64_t)(uintptr_t)dtr, t_code);
738 			(void) xge_hal_device_handle_tcode(channelh, dtr,
740 			xge_hal_ring_dtr_free(channelh, dtr); /* drop it */
752 			xge_hal_ring_dtr_free(channelh, dtr); /* drop it */
769 		xge_hal_ring_dtr_free(channelh, dtr);
843 	} while (xge_hal_ring_dtr_next_completed(channelh, &dtr, &t_code) ==
894 xgell_xmit_compl(xge_hal_channel_h channelh, xge_hal_dtr_h dtr, u8 t_code,
902 		    xge_hal_fifo_dtr_private(dtr));
906 			xge_debug_ll(XGE_TRACE, "%s%d: tx: dtr 0x%"PRIx64
908 			    lldev->instance, (uint64_t)(uintptr_t)dtr, t_code);
910 			(void) xge_hal_device_handle_tcode(channelh, dtr,
925 		xge_hal_fifo_dtr_free(channelh, dtr);
932 	} while (xge_hal_fifo_dtr_next_completed(channelh, &dtr, &t_code) ==
949 	xge_hal_dtr_h dtr;
982 	status = xge_hal_fifo_dtr_reserve(ring->channelh, &dtr);
1004 	txd_priv = xge_hal_fifo_dtr_private(dtr);
1027 	 *	xge_hal_fifo_dtr_vlan_set(dtr, tci);
1055 			    dtr, bp->b_rptr, mblen);
1062 				    ring->channelh, dtr, frag_cnt++);
1067 			    dtr, frag_cnt++);
1120 			xge_hal_fifo_dtr_buffer_set(ring->channelh, dtr,
1153 		xge_hal_fifo_dtr_buffer_finalize(ring->channelh, dtr,
1160 	 * If LSO is required, just call xge_hal_fifo_dtr_mss_set(dtr, mss) to
1167 		xge_hal_fifo_dtr_mss_set(dtr, mss);
1172 		xge_hal_fifo_dtr_cksum_set_bits(dtr,
1176 		xge_hal_fifo_dtr_cksum_set_bits(dtr, XGE_HAL_TXD_TX_CKO_TCP_EN |
1180 	xge_hal_fifo_dtr_post(ring->channelh, dtr);
1199 	xge_hal_fifo_dtr_free(ring->channelh, dtr);