Lines Matching defs:bit
1564 * for this packet. The Interrupt Control (IC) bit in the transmit
1567 * more obscure interrupt suppress bit which is probably part of the
1999 * 48-bit Ethernet address. Incoming frames with multicast destination
2005 * significant 9 bits of the result as a bit index into the table. If the
2006 * indexed bit is set, the frame is accepted. If the bit is cleared, the frame
2019 * matching cell address (index) and compares this to the bit position in the
2020 * cam mask. If the bit is set, the packet is passed up. If CAM lookup does not
2087 * Disable the corresponding mask bit.
2123 * Turn bit[crc_index] on.
2131 * Turn bit[crc_index] off.
2168 * The MSB first order is a bit odd because Ethernet standard is LSB first
2175 uint32_t bit;
2181 for (bit = 0; bit < 8; bit++) {
2527 * (after 512 bit times).
2863 * Request a pause of FFFF bit-times. This long pause
3014 * This bit will be cleared when the read is finished.
3057 * This bit will be cleared when the write is finished.