Lines Matching defs:bit
935 /* 32 bit addressing */
1977 * The interrupt routing bit should not be set.
1981 "ohci_take_control: Routing bit set");
3514 /* Add bit-stuffing overhead */
4196 * Modify the sKip bit on the Host Controller (HC) Endpoint Descriptor (ED).
4215 * If the skip bit is to be cleared, just clear it.
4217 * If the host controller reads the bit before the
4218 * driver has a chance to set the bit, the bit will
4228 /* Check Halt or Skip bit is already set */
4234 "Halt or Skip bit is already set");
4237 * The action is to set the skip bit. In order to
4238 * be sure that the HCD has seen the sKip bit, wait
4604 /* Store 32bit ID */
5063 * Only set the round bit on the last TD, to ensure
6991 /* Get and Store 32bit ID */
7225 /* Get and Store 32bit ID */
7391 * Set the sKip bit to stop all transactions on
7644 /* Free 32bit ID */
7734 * - First Host controller (HC) checks whether WDH bit
7737 * - If WDH bit is cleared then HC writes new done head
7740 * - Set WDH bit in the interrupt status register.
7745 * done head and WDH bit may be set or may not be set
7749 * HC has updated HCCA done head and WDH bit in ohci
7752 * - If done head is non-null and if WDH bit is not set
7754 * WDH bit in the interrupt stats register in between
7756 * head. In that case, definitely WDH bit will be set
7786 * intr bit is cleared.
7790 /* Set the WriteDoneHead bit in the interrupt events */
7794 /* Clear the WriteDoneHead bit */
7871 * interrupt bit in the interrupt status register.
8250 /* Free 32bit ID */
8666 /* Clear the halt bit */
9602 * bit must be faked on a control read.
10286 uint_t bit = 0;
10297 bit = ((eptd->bmAttributes &
10302 (Get_OpReg(hcr_control) & ~(bit)));
10313 * Set the sKip bit to stop all transactions on
10371 * Clear the sKip bit to restart all the
10679 * Restore the data toggle bit depending on the