Lines Matching defs:ural_write

382 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
402 "ural_write(): could not write MAC register:"
934 ural_write(sc, RAL_PHY_CSR7, tmp);
944 ural_write(sc, RAL_PHY_CSR7, val);
975 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff);
976 ural_write(sc, RAL_PHY_CSR10, tmp >> 16);
1119 ural_write(sc, RAL_TXRX_CSR19, 0);
1122 ural_write(sc, RAL_TXRX_CSR18, tmp);
1127 ural_write(sc, RAL_TXRX_CSR20, tmp);
1135 ural_write(sc, RAL_TXRX_CSR19, tmp);
1166 ural_write(sc, RAL_MAC_CSR10, slottime);
1167 ural_write(sc, RAL_MAC_CSR11, sifs);
1168 ural_write(sc, RAL_MAC_CSR12, eifs);
1182 ural_write(sc, RAL_TXRX_CSR10, tmp);
1193 ural_write(sc, RAL_TXRX_CSR11, 0x3);
1196 ural_write(sc, RAL_TXRX_CSR11, 0x150);
1199 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
1209 ural_write(sc, RAL_MAC_CSR5, tmp);
1212 ural_write(sc, RAL_MAC_CSR6, tmp);
1215 ural_write(sc, RAL_MAC_CSR7, tmp);
1226 ural_write(sc, RAL_MAC_CSR2, tmp);
1229 ural_write(sc, RAL_MAC_CSR3, tmp);
1232 ural_write(sc, RAL_MAC_CSR4, tmp);
1249 ural_write(sc, RAL_TXRX_CSR2, tmp);
1341 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));
1344 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));
1407 ural_write(sc, RAL_TXRX_CSR19, 0);
1409 ural_write(sc, RAL_MAC_CSR20, 0);
1441 ural_write(sc, RAL_MAC_CSR20, 1);
1655 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);
1658 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);
1659 ural_write(sc, RAL_MAC_CSR1, 0);
1674 ural_write(sc, 0x308, 0x00f0); /* magic */
1680 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
1697 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);
1700 ural_write(sc, RAL_TXRX_CSR11, 0x15f);
1736 ural_write(sc, RAL_TXRX_CSR2, tmp);