Lines Matching refs:sep
74 _sfxge_ev_qctor(sfxge_t *sp, sfxge_evq_t *sep, int kmflags, uint16_t evq_size)
76 efsys_mem_t *esmp = &(sep->se_mem);
81 EFX_STATIC_ASSERT(sizeof (sep->__se_u1.__se_s1) <=
82 sizeof (sep->__se_u1.__se_pad));
83 EFX_STATIC_ASSERT(sizeof (sep->__se_u2.__se_s2) <=
84 sizeof (sep->__se_u2.__se_pad));
85 EFX_STATIC_ASSERT(sizeof (sep->__se_u3.__se_s3) <=
86 sizeof (sep->__se_u3.__se_pad));
88 bzero(sep, sizeof (sfxge_evq_t));
90 sep->se_sp = sp;
108 &(sep->se_id))) != 0)
111 sep->se_stpp = &(sep->se_stp);
125 sep->se_sp = NULL;
127 SFXGE_OBJ_CHECK(sep, sfxge_evq_t);
135 sfxge_evq_t *sep = buf;
137 return (_sfxge_ev_qctor(sp, sep, kmflags, sp->s_evq0_size));
143 sfxge_evq_t *sep = buf;
145 return (_sfxge_ev_qctor(sp, sep, kmflags, sp->s_evqX_size));
148 _sfxge_ev_qdtor(sfxge_t *sp, sfxge_evq_t *sep, uint16_t evq_size)
150 efsys_mem_t *esmp = &(sep->se_mem);
151 ASSERT3P(sep->se_sp, ==, sp);
152 ASSERT3P(sep->se_stpp, ==, &(sep->se_stp));
153 sep->se_stpp = NULL;
156 sfxge_sram_buf_tbl_free(sp, sep->se_id, EFX_EVQ_NBUFS(evq_size));
157 sep->se_id = 0;
162 sep->se_sp = NULL;
164 SFXGE_OBJ_CHECK(sep, sfxge_evq_t);
170 sfxge_evq_t *sep = buf;
172 _sfxge_ev_qdtor(sp, sep, sp->s_evq0_size);
178 sfxge_evq_t *sep = buf;
180 _sfxge_ev_qdtor(sp, sep, sp->s_evqX_size);
186 sfxge_evq_t *sep = arg;
188 ASSERT(mutex_owned(&(sep->se_lock)));
191 if (sep->se_state == SFXGE_EVQ_STARTED)
194 ASSERT3U(sep->se_state, ==, SFXGE_EVQ_STARTING);
195 sep->se_state = SFXGE_EVQ_STARTED;
197 cv_broadcast(&(sep->se_init_kv));
204 sfxge_ev_qcomplete(sfxge_evq_t *sep, boolean_t eop)
206 sfxge_t *sp = sep->se_sp;
207 unsigned int index = sep->se_index;
211 if ((stp = sep->se_stp) != NULL) {
212 sep->se_stp = NULL;
213 sep->se_stpp = &(sep->se_stp);
240 sfxge_evq_t *sep = arg;
241 sfxge_t *sp = sep->se_sp;
248 ASSERT(mutex_owned(&(sep->se_lock)));
250 if (sep->se_exception)
257 ASSERT3U(sep->se_index, ==, srp->sr_index);
281 sep->se_exception = B_TRUE;
311 sep->se_rx++;
317 sfxge_ev_qcomplete(sep, B_FALSE);
321 return (sep->se_rx >= sep->se_ev_batch);
327 sfxge_evq_t *sep = arg;
328 sfxge_t *sp = sep->se_sp;
333 ASSERT(mutex_owned(&(sep->se_lock)));
334 sep->se_exception = B_TRUE;
351 sfxge_evq_t *sep_targetq, *sep = arg;
352 sfxge_t *sp = sep->se_sp;
358 ASSERT(mutex_owned(&(sep->se_lock)));
367 if (index == sep->se_index) {
391 sfxge_evq_t *sep_targetq, *sep = arg;
392 sfxge_t *sp = sep->se_sp;
398 ASSERT(mutex_owned(&(sep->se_lock)));
407 if (index == sep->se_index) {
431 sfxge_evq_t *sep = arg;
436 ASSERT(mutex_owned(&(sep->se_lock)));
438 stp = sep->se_label_stp[label];
445 ASSERT3U(sep->se_index, ==, stp->st_evq);
453 sep->se_tx++;
456 sep->se_stpp != &(stp->st_next)) {
457 *(sep->se_stpp) = stp;
458 sep->se_stpp = &(stp->st_next);
469 return (sep->se_tx >= sep->se_ev_batch);
475 sfxge_evq_t *sep = arg;
476 sfxge_t *sp = sep->se_sp;
482 ASSERT(mutex_owned(&(sep->se_lock)));
491 if (evq == sep->se_index) {
497 sep = sp->s_sep[evq];
504 ASSERT3U(sep->se_state, ==, SFXGE_EVQ_STARTED);
505 efx_ev_qpost(sep->se_eep, magic);
514 sfxge_evq_t *sep = arg;
515 sfxge_t *sp = sep->se_sp;
519 ASSERT(mutex_owned(&(sep->se_lock)));
534 ASSERT3U(sep->se_index, ==, srp->sr_index);
544 ASSERT3U(sep->se_index, ==, srp->sr_index);
554 ASSERT3U(sep->se_index, ==, srp->sr_index);
561 sfxge_txq_t *stp = sep->se_label_stp[label];
564 ASSERT3U(sep->se_index, ==, stp->st_evq);
624 sfxge_evq_t *sep = arg;
625 sfxge_t *sp = sep->se_sp;
635 sfxge_evq_t *sep = ksp->ks_private;
644 ASSERT(mutex_owned(&(sep->se_lock)));
646 if (sep->se_state != SFXGE_EVQ_STARTED)
649 efx_ev_qstats_update(sep->se_eep, sep->se_stat);
654 knp->value.ui64 = sep->se_cpu_id;
666 sfxge_ev_kstat_init(sfxge_evq_t *sep)
668 sfxge_t *sp = sep->se_sp;
669 unsigned int index = sep->se_index;
689 sep->se_ksp = ksp;
692 ksp->ks_private = sep;
693 ksp->ks_lock = &(sep->se_lock);
696 sep->se_stat = knp = ksp->ks_data;
715 sfxge_ev_kstat_fini(sfxge_evq_t *sep)
718 kstat_delete(sep->se_ksp);
719 sep->se_ksp = NULL;
720 sep->se_stat = NULL;
733 sfxge_evq_t *sep;
738 sep = kmem_cache_alloc(index ? sp->s_eqXc : sp->s_eq0c, KM_SLEEP);
739 if (sep == NULL) {
743 ASSERT3U(sep->se_state, ==, SFXGE_EVQ_UNINITIALIZED);
745 sep->se_index = index;
747 mutex_init(&(sep->se_lock), NULL,
750 cv_init(&(sep->se_init_kv), NULL, CV_DRIVER, NULL);
753 if ((rc = sfxge_ev_kstat_init(sep)) != 0)
756 sep->se_state = SFXGE_EVQ_INITIALIZED;
757 sep->se_ev_batch = (uint16_t)ev_batch;
758 sp->s_sep[index] = sep;
765 sep->se_index = 0;
767 cv_destroy(&(sep->se_init_kv));
768 mutex_destroy(&(sep->se_lock));
770 kmem_cache_free(index ? sp->s_eqXc : sp->s_eq0c, sep);
781 sfxge_evq_t *sep = sp->s_sep[index];
790 mutex_enter(&(sep->se_lock));
791 esmp = &(sep->se_mem);
793 ASSERT3U(sep->se_state, ==, SFXGE_EVQ_INITIALIZED);
799 if ((rc = sfxge_sram_buf_tbl_set(sp, sep->se_id, esmp,
804 eecp = &(sep->se_eec);
819 if ((rc = efx_ev_qcreate(enp, index, esmp, evq_size, sep->se_id,
820 &(sep->se_eep))) != 0)
824 if ((rc = efx_ev_qmoderate(sep->se_eep, sp->s_ev_moderation)) != 0)
833 sep->se_state = SFXGE_EVQ_STARTING;
836 if ((rc = efx_ev_qprime(sep->se_eep, sep->se_count)) != 0)
841 while (sep->se_state != SFXGE_EVQ_STARTED) {
842 if (cv_timedwait(&(sep->se_init_kv), &(sep->se_lock),
856 mutex_exit(&(sep->se_lock));
865 sep->se_state = SFXGE_EVQ_INITIALIZED;
874 efx_ev_qdestroy(sep->se_eep);
875 sep->se_eep = NULL;
881 bzero(&(sep->se_eec), sizeof (efx_ev_callbacks_t));
884 sfxge_sram_buf_tbl_clear(sp, sep->se_id, EFX_EVQ_NBUFS(evq_size));
889 mutex_exit(&(sep->se_lock));
897 sfxge_evq_t *sep = sp->s_sep[index];
902 mutex_enter(&(sep->se_lock));
904 if (sep->se_state != SFXGE_EVQ_STARTING &&
905 sep->se_state != SFXGE_EVQ_STARTED) {
913 if (cpu_id != sep->se_cpu_id) {
914 sep->se_cpu_id = cpu_id;
922 (void) ddi_dma_sync(sep->se_mem.esm_dma_handle,
927 ASSERT3U(sep->se_rx, ==, 0);
928 ASSERT3U(sep->se_tx, ==, 0);
929 ASSERT3P(sep->se_stp, ==, NULL);
930 ASSERT3P(sep->se_stpp, ==, &(sep->se_stp));
933 efx_ev_qpoll(sep->se_eep, &(sep->se_count), &(sep->se_eec),
934 sep);
936 sep->se_rx = 0;
937 sep->se_tx = 0;
940 sfxge_ev_qcomplete(sep, B_TRUE);
943 if ((rc = efx_ev_qprime(sep->se_eep, sep->se_count)) != 0)
946 mutex_exit(&(sep->se_lock));
955 mutex_exit(&(sep->se_lock));
963 sfxge_evq_t *sep = sp->s_sep[index];
966 mutex_enter(&(sep->se_lock));
968 if (sep->se_state != SFXGE_EVQ_STARTING &&
969 sep->se_state != SFXGE_EVQ_STARTED) {
974 if ((rc = efx_ev_qprime(sep->se_eep, sep->se_count)) != 0)
977 mutex_exit(&(sep->se_lock));
986 mutex_exit(&(sep->se_lock));
995 sfxge_evq_t *sep = sp->s_sep[index];
996 efx_evq_t *eep = sep->se_eep;
998 ASSERT3U(sep->se_state, ==, SFXGE_EVQ_STARTED);
1006 sfxge_evq_t *sep = sp->s_sep[index];
1009 mutex_enter(&(sep->se_lock));
1010 ASSERT3U(sep->se_state, ==, SFXGE_EVQ_STARTED);
1011 sep->se_state = SFXGE_EVQ_INITIALIZED;
1015 sep->se_cpu_id = 0;
1018 sep->se_count = 0;
1021 sep->se_exception = B_FALSE;
1024 efx_ev_qdestroy(sep->se_eep);
1025 sep->se_eep = NULL;
1027 mutex_exit(&(sep->se_lock));
1030 bzero(&(sep->se_eec), sizeof (efx_ev_callbacks_t));
1033 sfxge_sram_buf_tbl_clear(sp, sep->se_id, EFX_EVQ_NBUFS(evq_size));
1039 sfxge_evq_t *sep = sp->s_sep[index];
1041 ASSERT3U(sep->se_state, ==, SFXGE_EVQ_INITIALIZED);
1044 sep->se_state = SFXGE_EVQ_UNINITIALIZED;
1047 sfxge_ev_kstat_fini(sep);
1049 cv_destroy(&(sep->se_init_kv));
1050 mutex_destroy(&(sep->se_lock));
1052 sep->se_index = 0;
1054 kmem_cache_free(index ? sp->s_eqXc : sp->s_eq0c, sep);
1061 sfxge_evq_t *sep = sp->s_sep[evq];
1066 mutex_enter(&(sep->se_lock));
1075 if (sep->se_label_stp[label] == stp) {
1079 if ((stpp == NULL) && (sep->se_label_stp[label] == NULL)) {
1080 stpp = &sep->se_label_stp[label];
1088 label = stpp - sep->se_label_stp;
1093 mutex_exit(&(sep->se_lock));
1103 mutex_exit(&(sep->se_lock));
1113 sfxge_evq_t *sep = sp->s_sep[evq];
1116 mutex_enter(&(sep->se_lock));
1123 if (sep->se_label_stp[label] != stp) {
1127 sep->se_label_stp[label] = NULL;
1129 mutex_exit(&(sep->se_lock));
1138 mutex_exit(&(sep->se_lock));