Cross Reference: /illumos-gate/usr/src/uts/common/io/sfxge/common/siena

Lines Matching defs:stat
465 	__inout_ecount_opt(EFX_PHY_NSTATS)	uint32_t *stat)
471 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);
472 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);
473 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);
474 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);
481 		if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
487 			stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;
488 			stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;
489 			stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;
490 			stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;
494 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,
496 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,
498 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,
500 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,
503 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);
504 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);
505 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);
506 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);
507 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);
509 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,
511 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,
513 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,
515 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,
523 		if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
528 			stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;
529 			stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;
530 			stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;
531 			stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;
535 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);
536 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);
538 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,
549 	__inout_ecount(EFX_PHY_NSTATS)		uint32_t *stat)
579 	siena_phy_decode_stats(enp, vmask, esmp, &smask, stat);