Lines Matching refs:dp
181 static void sfe_set_eq_sis630(struct gem_dev *dp);
195 static int sfe_tx_desc_write(struct gem_dev *dp, int slot,
197 static void sfe_tx_start(struct gem_dev *dp, int startslot, int nslot);
198 static void sfe_rx_desc_write(struct gem_dev *dp, int slot,
200 static uint_t sfe_tx_desc_stat(struct gem_dev *dp, int slot, int ndesc);
201 static uint64_t sfe_rx_desc_stat(struct gem_dev *dp, int slot, int ndesc);
203 static void sfe_tx_desc_init(struct gem_dev *dp, int slot);
204 static void sfe_rx_desc_init(struct gem_dev *dp, int slot);
205 static void sfe_tx_desc_clean(struct gem_dev *dp, int slot);
206 static void sfe_rx_desc_clean(struct gem_dev *dp, int slot);
209 static uint_t sfe_interrupt(struct gem_dev *dp);
266 #define SFE_EEPROM_DELAY(dp) \
267 { (void) INL(dp, EROMAR); (void) INL(dp, EROMAR); }
272 sfe_read_eeprom(struct gem_dev *dp, uint_t offset)
279 OUTL(dp, EROMAR, 0);
280 SFE_EEPROM_DELAY(dp);
281 OUTL(dp, EROMAR, EROMAR_EESK);
282 SFE_EEPROM_DELAY(dp);
292 OUTL(dp, EROMAR, EROMAR_EECS | eedi);
293 SFE_EEPROM_DELAY(dp);
294 OUTL(dp, EROMAR, EROMAR_EECS | eedi | EROMAR_EESK);
295 SFE_EEPROM_DELAY(dp);
298 OUTL(dp, EROMAR, EROMAR_EECS);
303 OUTL(dp, EROMAR, EROMAR_EECS);
304 SFE_EEPROM_DELAY(dp);
305 OUTL(dp, EROMAR, EROMAR_EECS | EROMAR_EESK);
306 SFE_EEPROM_DELAY(dp);
308 ret = (ret << 1) | ((INL(dp, EROMAR) >> EROMAR_EEDO_SHIFT) & 1);
311 OUTL(dp, EROMAR, 0);
312 SFE_EEPROM_DELAY(dp);
319 sfe_get_mac_addr_dp83815(struct gem_dev *dp)
327 DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
329 mac = dp->dev_addr.ether_addr_octet;
335 val = sfe_read_eeprom(dp, 0x6);
339 val = sfe_read_eeprom(dp, 0x7);
345 val = sfe_read_eeprom(dp, 0x8);
351 val = sfe_read_eeprom(dp, 0x9);
361 sfe_get_mac_addr_sis900(struct gem_dev *dp)
367 mac = dp->dev_addr.ether_addr_octet;
370 val = sfe_read_eeprom(dp, 0x8 + i);
422 sfe_get_mac_addr_sis630e(struct gem_dev *dp)
436 dp->name);
442 dp->name);
452 dp->dev_addr.ether_addr_octet[i] = inb(0x71);
463 sfe_get_mac_addr_sis635(struct gem_dev *dp)
468 struct sfe_dev *lp = dp->private;
470 DPRINTF(2, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
471 rfcr = INL(dp, RFCR);
473 OUTL(dp, CR, lp->cr | CR_RELOAD);
474 OUTL(dp, CR, lp->cr);
477 OUTL(dp, RFCR, rfcr & ~RFCR_RFEN);
481 OUTL(dp, RFCR,
483 v = INL(dp, RFDR);
484 dp->dev_addr.ether_addr_octet[i] = (uint8_t)v;
485 dp->dev_addr.ether_addr_octet[i+1] = (uint8_t)(v >> 8);
489 OUTL(dp, RFCR, rfcr | RFCR_RFEN);
495 sfe_get_mac_addr_sis962(struct gem_dev *dp)
503 OUTL(dp, MEAR, EROMAR_EEREQ);
504 for (i = 0; (INL(dp, MEAR) & EROMAR_EEGNT) == 0; i++) {
508 CONS "%s: failed to access eeprom", dp->name);
513 ret = sfe_get_mac_addr_sis900(dp);
516 OUTL(dp, MEAR, EROMAR_EEDONE);
522 sfe_reset_chip_sis900(struct gem_dev *dp)
527 struct sfe_dev *lp = dp->private;
529 DPRINTF(4, (CE_CONT, CONS "%s: %s called", dp->name, __func__));
537 OUTL(dp, IMR, 0);
538 lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits;
540 OUTLINL(dp, RFCR, 0);
542 OUTL(dp, CR, CR_RST | CR_TXR | CR_RXR);
548 cmn_err(CE_WARN, "%s: chip reset timeout", dp->name);
551 done |= INL(dp, ISR) & (ISR_TXRCMP | ISR_RXRCMP);
557 OUTL(dp, CR, lp->cr | INL(dp, CR));
562 dp->name, INL(dp, CFG), CFG_BITS_SIS900));
569 OUTL(dp, CFG, val);
570 DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b", dp->name,
571 INL(dp, CFG), CFG_BITS_SIS900));
577 sfe_reset_chip_dp83815(struct gem_dev *dp)
581 struct sfe_dev *lp = dp->private;
583 DPRINTF(4, (CE_CONT, CONS "%s: %s called", dp->name, __func__));
591 OUTL(dp, IMR, 0);
592 lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits;
594 OUTL(dp, RFCR, 0);
596 OUTL(dp, CR, CR_RST);
599 for (i = 0; INL(dp, CR) & CR_RST; i++) {
601 cmn_err(CE_WARN, "!%s: chip reset timeout", dp->name);
606 DPRINTF(0, (CE_CONT, "!%s: chip reset in %duS", dp->name, i*10));
608 OUTL(dp, CCSR, CCSR_PMESTS);
609 OUTL(dp, CCSR, 0);
613 dp->name, INL(dp, CFG), CFG_BITS_DP83815));
614 val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG);
615 OUTL(dp, CFG, val | CFG_PAUSE_ADV);
616 DPRINTF(2, (CE_CONT, CONS "%s: cfg:%b", dp->name,
617 INL(dp, CFG), CFG_BITS_DP83815));
623 sfe_init_chip(struct gem_dev *dp)
632 OUTL(dp, IMR, 0);
637 OUTL(dp, TXDP, dp->tx_ring_dma);
640 OUTL(dp, RXDP, dp->rx_ring_dma);
646 sfe_mcast_hash(struct gem_dev *dp, uint8_t *addr)
653 sfe_rxfilter_dump(struct gem_dev *dp, int start, int end)
659 cmn_err(CE_CONT, "!%s: rx filter ram dump:", dp->name);
663 OUTL(dp, RFCR, RFADDR_MAC_DP83815 + i + j*2);
664 ram[j] = INL(dp, RFDR);
683 sfe_set_rx_filter_dp83815(struct gem_dev *dp)
688 uint8_t *mac = dp->cur_addr.ether_addr_octet;
690 struct sfe_dev *lp = dp->private;
693 dp->name, __func__, dp->mc_count, dp->rxmode, RXMODE_BITS));
696 for (i = 0; i < dp->mc_count; i++) {
699 dp->name, i,
700 dp->mc_list[i].addr.ether_addr_octet[0],
701 dp->mc_list[i].addr.ether_addr_octet[1],
702 dp->mc_list[i].addr.ether_addr_octet[2],
703 dp->mc_list[i].addr.ether_addr_octet[3],
704 dp->mc_list[i].addr.ether_addr_octet[4],
705 dp->mc_list[i].addr.ether_addr_octet[5]);
708 if ((dp->rxmode & RXMODE_ENABLE) == 0) {
710 OUTL(dp, RFCR, 0);
717 if (dp->rxmode & RXMODE_PROMISC) {
720 } else if ((dp->rxmode & RXMODE_ALLMULTI) || dp->mc_count > 16*32/2) {
723 } else if (dp->mc_count > 4) {
731 for (i = 0; i < dp->mc_count; i++) {
732 j = dp->mc_list[i].hash >> (32 - 9);
742 (((1 << dp->mc_count) - 1) << RFCR_APAT_SHIFT);
749 dp->name, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
761 OUTL(dp, RFCR, RFADDR_MAC_DP83815 + i);
762 OUTL(dp, RFDR, (mac[i+1] << 8) | mac[i]);
771 OUTL(dp, RFCR, j);
772 OUTL(dp, RFDR, 0);
777 for (j = 0; j < dp->mc_count; j++) {
778 mac = &dp->mc_list[j].addr.ether_addr_octet[0];
780 OUTL(dp, RFCR,
782 OUTL(dp, RFDR, (mac[i+1] << 8) | mac[i]);
787 OUTL(dp, RFCR, RFADDR_PCOUNT01_DP83815);
788 OUTL(dp, RFDR, (ETHERADDRL << 8) | ETHERADDRL);
789 OUTL(dp, RFCR, RFADDR_PCOUNT23_DP83815);
790 OUTL(dp, RFDR, (ETHERADDRL << 8) | ETHERADDRL);
797 OUTL(dp, RFCR, RFADDR_MULTICAST_DP83815 + i*2);
798 OUTL(dp, RFDR, hash_tbl[i]);
802 sfe_rxfilter_dump(dp, 0, 0x10);
803 sfe_rxfilter_dump(dp, 0x200, 0x380);
806 OUTL(dp, RFCR, RFCR_RFEN | mode);
812 sfe_set_rx_filter_sis900(struct gem_dev *dp)
817 uint8_t *mac = dp->cur_addr.ether_addr_octet;
820 struct sfe_dev *lp = dp->private;
822 DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
824 if ((dp->rxmode & RXMODE_ENABLE) == 0) {
826 OUTLINL(dp, RFCR, 0);
842 if (dp->rxmode & RXMODE_PROMISC) {
845 } else if ((dp->rxmode & RXMODE_ALLMULTI) ||
846 dp->mc_count > hash_size*16/2) {
855 for (i = 0; i < dp->mc_count; i++) {
857 h = dp->mc_list[i].hash >> hash_shift;
865 OUTLINL(dp, RFCR,
867 OUTLINL(dp, RFDR, (mac[i*2+1] << 8) | mac[i*2]);
876 OUTLINL(dp, RFCR,
878 OUTLINL(dp, RFDR, hash_tbl[i]);
882 OUTLINL(dp, RFCR, RFCR_RFEN | mode);
888 sfe_start_chip(struct gem_dev *dp)
890 struct sfe_dev *lp = dp->private;
892 DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
901 if ((dp->misc_flag & GEM_NOINTR) == 0) {
902 OUTL(dp, IER, 1);
903 OUTL(dp, IMR, lp->our_intr_bits);
907 OUTL(dp, CR, lp->cr | CR_RXE);
916 sfe_stop_chip(struct gem_dev *dp)
918 struct sfe_dev *lp = dp->private;
923 DPRINTF(4, (CE_CONT, CONS "%s: %s: called", dp->name, __func__));
929 OUTL(dp, IMR, 0);
932 OUTL(dp, CR, lp->cr | CR_TXR | CR_RXR);
942 dp->name, __func__);
946 val = INL(dp, ISR);
960 sfe_stop_chip_quiesce(struct gem_dev *dp)
962 struct sfe_dev *lp = dp->private;
971 OUTL(dp, IMR, 0);
974 OUTL(dp, CR, CR_TXR | CR_RXR);
986 val = INL(dp, ISR);
1020 sfe_set_media(struct gem_dev *dp)
1028 struct sfe_dev *lp = dp->private;
1033 dp->name, __func__,
1034 dp->full_duplex ? "full" : "half", gem_speed_value[dp->speed]));
1038 if (dp->full_duplex) {
1042 if (dp->full_duplex) {
1051 val = INL(dp, CFG) & CFG_EDB_MASTER;
1074 txmxdma = max(dp->txmaxdma, 256);
1075 rxmxdma = max(dp->rxmaxdma, 256);
1080 lp->tx_drain_threshold = ROUNDUP2(dp->txthr, TXCFG_FIFO_UNIT);
1106 val = ROUNDUP2(max(dp->rxthr, ETHERMIN), RXCFG_FIFO_UNIT);
1113 dp->name, __func__,
1124 OUTL(dp, TXCFG, txcfg);
1130 OUTL(dp, RXCFG, rxcfg);
1133 dp->name, __func__,
1138 pcr = INL(dp, PCR);
1139 switch (dp->flow_control) {
1142 OUTL(dp, PCR, pcr | PCR_PSEN | PCR_PS_MCAST);
1146 OUTL(dp, PCR,
1150 DPRINTF(2, (CE_CONT, CONS "%s: PCR: %b", dp->name,
1151 INL(dp, PCR), PCR_BITS));
1154 switch (dp->flow_control) {
1157 OUTL(dp, FLOWCTL, FLOWCTL_FLOWEN);
1160 OUTL(dp, FLOWCTL, 0);
1164 dp->name, INL(dp, FLOWCTL), FLOWCTL_BITS));
1170 sfe_get_stats(struct gem_dev *dp)
1180 sfe_tx_desc_write(struct gem_dev *dp, int slot,
1192 dp->name, ddi_get_lbolt(), __func__,
1193 dp->tx_desc_tail, slot, frags, flags);
1215 tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot];
1225 sfe_tx_start(struct gem_dev *dp, int start_slot, int nslot)
1227 uint_t tx_ring_size = dp->gc.gc_tx_ring_size;
1229 struct sfe_dev *lp = dp->private;
1232 gem_tx_desc_dma_sync(dp,
1237 tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * start_slot];
1240 gem_tx_desc_dma_sync(dp, start_slot, 1, DDI_DMA_SYNC_FORDEV);
1245 if (dp->mac_active) {
1246 OUTL(dp, CR, lp->cr | CR_TXE);
1251 sfe_rx_desc_write(struct gem_dev *dp, int slot,
1264 dp->name, __func__, dp->rx_active_tail, slot, frags);
1271 rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot];
1280 sfe_tx_desc_stat(struct gem_dev *dp, int slot, int ndesc)
1282 uint_t tx_ring_size = dp->gc.gc_tx_ring_size;
1286 struct sfe_dev *lp = dp->private;
1293 &dp->tx_ring[SFE_DESC_SIZE * SLOT(slot + ndesc - 1, tx_ring_size)];
1303 dp->name, ddi_get_lbolt(), __func__,
1312 dp->mac_active) {
1313 OUTL(dp, CR, lp->cr | CR_TXE);
1323 dp->name, slot, status);
1327 delay = (ddi_get_lbolt() - dp->tx_buf_head->txb_stime) * 10;
1330 dp->name, delay, slot));
1342 &dp->tx_ring[SFE_DESC_SIZE * n]))->d_cmdsts);
1357 dp->name, status, TXSTAT_BITS));
1359 dp->stats.errxmt++;
1362 dp->stats.underflow++;
1364 dp->stats.nocarrier++;
1366 dp->stats.xmtlatecoll++;
1367 } else if ((!dp->full_duplex) && (status & CMDSTS_EC)) {
1368 dp->stats.excoll++;
1369 dp->stats.collisions += 16;
1371 dp->stats.xmit_internal_err++;
1373 } else if (!dp->full_duplex) {
1378 dp->stats.first_coll++;
1380 dp->stats.multi_coll++;
1382 dp->stats.collisions += cols;
1384 dp->stats.defer++;
1391 sfe_rx_desc_stat(struct gem_dev *dp, int slot, int ndesc)
1402 rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot];
1412 dp->name, ddi_get_lbolt(), __func__,
1433 dp->name, status, RXSTAT_BITS));
1436 dp->stats.errrcv++;
1439 dp->stats.overflow++;
1441 dp->stats.frame_too_long++;
1443 dp->stats.runt++;
1445 dp->stats.frame++;
1447 dp->stats.crc++;
1449 dp->stats.rcv_internal_err++;
1465 uint8_t *bp = dp->rx_buf_head->rxb_buf;
1467 cmn_err(CE_CONT, CONS "%s: len:%d", dp->name, len);
1482 sfe_tx_desc_init(struct gem_dev *dp, int slot)
1484 uint_t tx_ring_size = dp->gc.gc_tx_ring_size;
1488 tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot];
1494 here = ((uint32_t)dp->tx_ring_dma) + SFE_DESC_SIZE*slot;
1497 &dp->tx_ring[SFE_DESC_SIZE * SLOT(slot - 1, tx_ring_size)];
1502 sfe_rx_desc_init(struct gem_dev *dp, int slot)
1504 uint_t rx_ring_size = dp->gc.gc_rx_ring_size;
1508 rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot];
1514 here = ((uint32_t)dp->rx_ring_dma) + SFE_DESC_SIZE*slot;
1517 &dp->rx_ring[SFE_DESC_SIZE * SLOT(slot - 1, rx_ring_size)];
1522 sfe_tx_desc_clean(struct gem_dev *dp, int slot)
1526 tdp = (void *)&dp->tx_ring[SFE_DESC_SIZE * slot];
1531 sfe_rx_desc_clean(struct gem_dev *dp, int slot)
1535 rdp = (void *)&dp->rx_ring[SFE_DESC_SIZE * slot];
1543 sfe_interrupt(struct gem_dev *dp)
1545 uint_t rx_ring_size = dp->gc.gc_rx_ring_size;
1550 struct sfe_dev *lp = dp->private;
1553 isr = INL(dp, ISR);
1565 dp->name, ddi_get_lbolt(), __func__,
1566 isr, INTR_BITS, dp->rx_active_head));
1568 if (!dp->mac_active) {
1578 (void) gem_receive(dp);
1583 dp->name, isr, INTR_BITS));
1585 dp->stats.overflow++;
1591 dp->name, isr, INTR_BITS));
1593 dp->stats.norcvbuf++;
1599 OUTL(dp, RXDP, dp->rx_ring_dma +
1601 SLOT(dp->rx_active_head, rx_ring_size));
1604 OUTL(dp, CR, lp->cr | CR_RXE);
1611 if (gem_tx_done(dp)) {
1622 dp->name, isr, INTR_BITS);
1627 (void) gem_restart_nic(dp, GEM_RESTART_KEEP_BUF);
1632 dp->name, __func__, isr, INTR_BITS));
1647 sfe_mii_sync_dp83815(struct gem_dev *dp)
1653 sfe_mii_read_dp83815(struct gem_dev *dp, uint_t offset)
1656 dp->name, __func__, offset));
1657 return ((uint16_t)INL(dp, MII_REGS_BASE + offset*4));
1661 sfe_mii_write_dp83815(struct gem_dev *dp, uint_t offset, uint16_t val)
1664 dp->name, __func__, offset, val));
1665 OUTL(dp, MII_REGS_BASE + offset*4, val);
1669 sfe_mii_config_dp83815(struct gem_dev *dp)
1673 srr = INL(dp, SRR) & SRR_REV;
1676 dp->name, srr,
1677 INW(dp, 0x00cc), /* PGSEL */
1678 INW(dp, 0x00e4), /* PMDCSR */
1679 INW(dp, 0x00fc), /* TSTDAT */
1680 INW(dp, 0x00f4), /* DSPCFG */
1681 INW(dp, 0x00f8))); /* SDCFG */
1690 OUTW(dp, 0x00cc, 0x0001); /* PGSEL */
1691 OUTW(dp, 0x00e4, 0x189c); /* PMDCSR */
1692 OUTW(dp, 0x00fc, 0x0000); /* TSTDAT */
1693 OUTW(dp, 0x00f4, 0x5040); /* DSPCFG */
1694 OUTW(dp, 0x00f8, 0x008c); /* SDCFG */
1695 OUTW(dp, 0x00cc, 0x0000); /* PGSEL */
1699 dp->name,
1700 INW(dp, 0x00cc), /* PGSEL */
1701 INW(dp, 0x00e4), /* PMDCSR */
1702 INW(dp, 0x00fc), /* TSTDAT */
1703 INW(dp, 0x00f4), /* DSPCFG */
1704 INW(dp, 0x00f8))); /* SDCFG */
1710 OUTW(dp, 0x00cc, 0x0001); /* PGSEL */
1711 OUTW(dp, 0x00e4, 0x189c); /* PMDCSR */
1712 OUTW(dp, 0x00cc, 0x0000); /* PGSEL */
1716 dp->name,
1717 INW(dp, 0x00cc), /* PGSEL */
1718 INW(dp, 0x00e4))); /* PMDCSR */
1721 return (gem_mii_config_default(dp));
1725 sfe_mii_probe_dp83815(struct gem_dev *dp)
1731 dp->name, __func__));
1732 dp->mii_phy_addr = 0;
1733 dp->gc.gc_mii_sync = &sfe_mii_sync_sis900;
1734 dp->gc.gc_mii_read = &sfe_mii_read_sis900;
1735 dp->gc.gc_mii_write = &sfe_mii_write_sis900;
1737 val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG);
1738 OUTL(dp, CFG, val | CFG_EXT_PHY | CFG_PHY_DIS);
1740 if (gem_mii_probe_default(dp) == GEM_SUCCESS) {
1746 dp->name, __func__));
1747 dp->mii_phy_addr = -1;
1748 dp->gc.gc_mii_sync = &sfe_mii_sync_dp83815;
1749 dp->gc.gc_mii_read = &sfe_mii_read_dp83815;
1750 dp->gc.gc_mii_write = &sfe_mii_write_dp83815;
1752 val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG);
1753 OUTL(dp, CFG, val | CFG_PAUSE_ADV | CFG_PHY_RST);
1755 OUTL(dp, CFG, val | CFG_PAUSE_ADV);
1760 return (gem_mii_probe_default(dp));
1764 sfe_mii_init_dp83815(struct gem_dev *dp)
1768 val = INL(dp, CFG) & (CFG_ANEG_SEL | CFG_PHY_CFG);
1770 if (dp->mii_phy_addr == -1) {
1772 OUTL(dp, CFG, val | CFG_PAUSE_ADV);
1775 OUTL(dp, CFG, val | CFG_EXT_PHY | CFG_PHY_DIS);
1784 #define MDIO_DELAY(dp) {(void) INL(dp, MEAR); (void) INL(dp, MEAR); }
1786 sfe_mii_sync_sis900(struct gem_dev *dp)
1792 OUTL(dp, MEAR, MEAR_MDDIR | MEAR_MDIO);
1793 MDIO_DELAY(dp);
1794 OUTL(dp, MEAR, MEAR_MDDIR | MEAR_MDIO | MEAR_MDC);
1795 MDIO_DELAY(dp);
1800 sfe_mii_config_sis900(struct gem_dev *dp)
1802 struct sfe_dev *lp = dp->private;
1805 if ((dp->mii_phy_id & PHY_MASK) == PHY_ICS1893) {
1807 gem_mii_write(dp, 0x0018, 0xD200);
1815 gem_mii_write(dp, MII_AN_ADVERT, 0x05e1);
1816 gem_mii_write(dp, MII_CONFIG1, 0x0022);
1817 gem_mii_write(dp, MII_CONFIG2, 0xff00);
1818 gem_mii_write(dp, MII_MASK, 0xffc0);
1820 sfe_set_eq_sis630(dp);
1822 return (gem_mii_config_default(dp));
1826 sfe_mii_read_sis900(struct gem_dev *dp, uint_t reg)
1833 cmd = MII_READ_CMD(dp->mii_phy_addr, reg);
1837 OUTL(dp, MEAR, data | MEAR_MDDIR);
1838 MDIO_DELAY(dp);
1839 OUTL(dp, MEAR, data | MEAR_MDDIR | MEAR_MDC);
1840 MDIO_DELAY(dp);
1844 OUTL(dp, MEAR, 0);
1845 MDIO_DELAY(dp);
1848 OUTL(dp, MEAR, MEAR_MDC);
1849 MDIO_DELAY(dp);
1851 OUTL(dp, MEAR, 0);
1853 (void) INL(dp, MEAR); /* delay */
1854 if (INL(dp, MEAR) & MEAR_MDIO) {
1856 dp->name, dp->mii_phy_addr);
1859 MDIO_DELAY(dp);
1862 OUTL(dp, MEAR, MEAR_MDC);
1863 MDIO_DELAY(dp);
1867 OUTL(dp, MEAR, 0);
1868 (void) INL(dp, MEAR); /* delay */
1869 ret = (ret << 1) | ((INL(dp, MEAR) >> MEAR_MDIO_SHIFT) & 1);
1870 OUTL(dp, MEAR, MEAR_MDC);
1871 MDIO_DELAY(dp);
1876 OUTL(dp, MEAR, 0);
1877 MDIO_DELAY(dp);
1878 OUTL(dp, MEAR, MEAR_MDC);
1879 MDIO_DELAY(dp);
1886 sfe_mii_write_sis900(struct gem_dev *dp, uint_t reg, uint16_t val)
1892 cmd = MII_WRITE_CMD(dp->mii_phy_addr, reg, val);
1896 OUTL(dp, MEAR, data | MEAR_MDDIR);
1897 MDIO_DELAY(dp);
1898 OUTL(dp, MEAR, data | MEAR_MDDIR | MEAR_MDC);
1899 MDIO_DELAY(dp);
1904 OUTL(dp, MEAR, 0);
1905 MDIO_DELAY(dp);
1906 OUTL(dp, MEAR, MEAR_MDC);
1907 MDIO_DELAY(dp);
1913 sfe_set_eq_sis630(struct gem_dev *dp)
1921 struct sfe_dev *lp = dp->private;
1931 if (dp->mii_state == MII_STATE_LINKUP) {
1932 reg14h = gem_mii_read(dp, MII_RESV);
1933 gem_mii_write(dp, MII_RESV, (0x2200 | reg14h) & 0xBFFF);
1935 eq_value = (0x00f8 & gem_mii_read(dp, MII_RESV)) >> 3;
1938 eq_value = (0x00f8 & gem_mii_read(dp, MII_RESV)) >> 3;
1971 reg14h = gem_mii_read(dp, MII_RESV) & ~0x02f8;
1973 gem_mii_write(dp, MII_RESV, reg14h);
1975 reg14h = (gem_mii_read(dp, MII_RESV) & ~0x4000) | 0x2000;
1982 gem_mii_write(dp, MII_RESV, reg14h);
1992 sfe_chipinfo_init_sis900(struct gem_dev *dp)
1995 struct sfe_dev *lp = (struct sfe_dev *)dp->private;
2026 dp->name);
2032 dp->name);
2043 sfe_attach_chip(struct gem_dev *dp)
2045 struct sfe_dev *lp = (struct sfe_dev *)dp->private;
2047 DPRINTF(4, (CE_CONT, CONS "!%s: %s called", dp->name, __func__));
2051 sfe_chipinfo_init_sis900(dp);
2057 if (!(lp->get_mac_addr)(dp)) {
2061 dp->name, __func__);
2066 dp->mii_phy_addr = -1; /* no need to scan PHY */
2067 dp->misc_flag |= GEM_VLAN_SOFT;
2068 dp->txthr += 4; /* VTAG_SIZE */
2070 dp->txthr = min(dp->txthr, TXFIFOSIZE - 2);
2090 struct gem_dev *dp;
2301 dp = gem_do_attach(dip, 0, gcp, base, ®s_ha,
2305 if (dp == NULL) {
2348 struct gem_dev *dp;
2351 dp = GEM_GET_DEV(dip);
2353 if (dp == NULL)
2356 ret = sfe_stop_chip_quiesce(dp);