Lines Matching refs:RT2661_WRITE
486 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
489 RT2661_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
490 RT2661_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
491 RT2661_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
494 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR,
502 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
505 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
1082 RT2661_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1085 RT2661_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1093 RT2661_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1095 RT2661_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1096 RT2661_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1097 RT2661_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1107 RT2661_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1132 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1133 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1136 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1137 RT2661_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1195 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1196 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1513 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << 0);
1636 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1738 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1755 RT2661_WRITE(sc, RT2661_MAC_CSR9, tmp);
1772 RT2661_WRITE(sc, RT2661_MAC_CSR9, tmp);
1796 RT2661_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1810 RT2661_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1821 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0x3);
1824 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0x150);
1827 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0xf);
1837 RT2661_WRITE(sc, RT2661_MAC_CSR4, tmp);
1840 RT2661_WRITE(sc, RT2661_MAC_CSR5, tmp);
1862 RT2661_WRITE(sc, RT2661_TXRX_CSR9, tmp);
2021 RT2661_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
2098 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2102 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2105 RT2661_WRITE(sc, RT2661_MAC_CSR1, 3);
2106 RT2661_WRITE(sc, RT2661_MAC_CSR1, 0);
2109 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
2110 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2113 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2114 RT2661_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2132 RT2661_WRITE(sc, RT2661_MAC_CSR2, tmp);
2135 RT2661_WRITE(sc, RT2661_MAC_CSR3, tmp);
2156 RT2661_WRITE(sc, RT2661_PHY_CSR3, val);
2226 RT2661_WRITE(sc, RT2661_PHY_CSR3, tmp);
2276 RT2661_WRITE(sc, RT2661_PHY_CSR0, tmp);
2295 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2301 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2323 RT2661_WRITE(sc, RT2661_PHY_CSR4, tmp);
2432 RT2661_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].paddr);
2433 RT2661_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].paddr);
2434 RT2661_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].paddr);
2435 RT2661_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].paddr);
2438 RT2661_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.paddr);
2441 RT2661_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.paddr);
2444 RT2661_WRITE(sc, RT2661_TX_RING_CSR0,
2450 RT2661_WRITE(sc, RT2661_TX_RING_CSR1,
2456 RT2661_WRITE(sc, RT2661_RX_RING_CSR,
2462 RT2661_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2465 RT2661_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2468 RT2661_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2472 RT2661_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2477 RT2661_WRITE(sc, RT2661_MAC_CSR1, 3);
2478 RT2661_WRITE(sc, RT2661_MAC_CSR1, 0);
2519 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2529 RT2661_WRITE(sc, RT2661_MAC_CSR1, 4);
2532 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2535 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2536 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2539 RT2661_WRITE(sc, RT2661_RX_CNTL_CSR, 1);