Lines Matching defs:sc
317 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
324 RT2661_EEPROM_CTL(sc, 0);
326 RT2661_EEPROM_CTL(sc, RT2661_S);
327 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
328 RT2661_EEPROM_CTL(sc, RT2661_S);
331 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
332 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
335 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
336 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
337 RT2661_EEPROM_CTL(sc, RT2661_S);
338 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
341 n = (RT2661_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
343 RT2661_EEPROM_CTL(sc, RT2661_S |
345 RT2661_EEPROM_CTL(sc, RT2661_S |
349 RT2661_EEPROM_CTL(sc, RT2661_S);
354 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
355 tmp = RT2661_READ(sc, RT2661_E2PROM_CSR);
357 RT2661_EEPROM_CTL(sc, RT2661_S);
360 RT2661_EEPROM_CTL(sc, 0);
363 RT2661_EEPROM_CTL(sc, RT2661_S);
364 RT2661_EEPROM_CTL(sc, 0);
365 RT2661_EEPROM_CTL(sc, RT2661_C);
372 rt2661_read_eeprom(struct rt2661_softc *sc)
374 struct ieee80211com *ic = &sc->sc_ic;
379 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
383 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
387 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
391 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
393 sc->rf_rev = (val >> 11) & 0x1f;
394 sc->hw_radio = (val >> 10) & 0x1;
395 sc->rx_ant = (val >> 4) & 0x3;
396 sc->tx_ant = (val >> 2) & 0x3;
397 sc->nb_ant = val & 0x3;
400 "RF revision=%d\n", sc->rf_rev);
402 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
403 sc->ext_5ghz_lna = (val >> 6) & 0x1;
404 sc->ext_2ghz_lna = (val >> 4) & 0x1;
408 sc->ext_2ghz_lna, sc->ext_5ghz_lna);
410 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
412 sc->rssi_2ghz_corr = (int8_t)(val & 0xff);
414 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
416 sc->rssi_5ghz_corr = (int8_t)(val & 0xff);
419 if (sc->ext_2ghz_lna)
420 sc->rssi_2ghz_corr -= 14;
421 if (sc->ext_5ghz_lna)
422 sc->rssi_5ghz_corr -= 14;
426 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr);
428 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
430 sc->rfprog = (val >> 8) & 0x3;
432 sc->rffreq = val & 0xff;
435 "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq);
439 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
440 sc->txpow[i * 2] = (int8_t)(val >> 8);
443 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]);
444 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff);
447 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]);
452 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
455 sc->bbp_prom[i].reg = val >> 8;
456 sc->bbp_prom[i].val = val & 0xff;
458 "BBP R%d=%02x\n", sc->bbp_prom[i].reg,
459 sc->bbp_prom[i].val);
476 rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode_p, int size)
486 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
489 RT2661_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
490 RT2661_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
491 RT2661_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
494 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR,
496 /* RT2661_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); */
499 RT2661_MEM_WRITE1(sc, off++, *fptr++);
502 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
505 RT2661_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
509 if (RT2661_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
608 rt2661_alloc_tx_ring(struct rt2661_softc *sc,
624 err = rt2661_alloc_dma_mem(sc->sc_dev, &rt2661_dma_attr, size,
648 err = rt2661_alloc_dma_mem(sc->sc_dev,
649 &rt2661_dma_attr, sc->sc_dmabuf_size,
682 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
700 if (!RT2661_IS_FASTREBOOT(sc))
712 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
737 rt2661_alloc_rx_ring(struct rt2661_softc *sc,
751 err = rt2661_alloc_dma_mem(sc->sc_dev, &rt2661_dma_attr, size,
775 err = rt2661_alloc_dma_mem(sc->sc_dev,
776 &rt2661_dma_attr, sc->sc_dmabuf_size,
810 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
817 if (!RT2661_IS_FASTREBOOT(sc))
827 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
847 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
866 0, sc->sc_dmabuf_size,
886 rt2661_tx_intr(struct rt2661_softc *sc)
888 struct ieee80211com *ic = &sc->sc_ic;
897 val = RT2661_READ(sc, RT2661_STA_CSR4);
903 ring = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
926 sc->sc_tx_retries++;
953 if (sc->sc_need_sched) {
954 sc->sc_need_sched = 0;
958 sc->sc_tx_timer = 0;
962 rt2661_rx_intr(struct rt2661_softc *sc)
964 struct ieee80211com *ic = &sc->sc_ic;
975 mutex_enter(&sc->sc_rxlock);
976 ring = &sc->rxq;
1002 sc->sc_rx_err++;
1007 sc->sc_rx_err++;
1012 0, sc->sc_dmabuf_size,
1019 (pktlen > sc->sc_dmabuf_size)) {
1022 sc->sc_rx_err++;
1029 sc->sc_rx_nobuf++;
1039 rssi = rt2661_get_rssi(sc, desc->rssi);
1043 sc->avg_rssi = (rssi + 7 * sc->avg_rssi) / 8;
1056 "rx intr idx=%u\n", sc->rxq.cur);
1059 mutex_exit(&sc->sc_rxlock);
1066 struct rt2661_softc *sc = (struct rt2661_softc *)data;
1068 if (sc->sc_rx_pend) {
1069 sc->sc_rx_pend = 0;
1070 rt2661_rx_intr(sc);
1077 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
1079 if (RT2661_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
1082 RT2661_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1085 RT2661_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1091 rt2661_mcu_wakeup(struct rt2661_softc *sc)
1093 RT2661_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1095 RT2661_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1096 RT2661_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1097 RT2661_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1100 (void) rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1104 rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1106 (void) RT2661_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1107 RT2661_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1114 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
1117 RT2661_GLOCK(sc);
1119 if (!RT2661_IS_RUNNING(sc) || RT2661_IS_SUSPEND(sc)) {
1120 RT2661_GUNLOCK(sc);
1124 r1 = RT2661_READ(sc, RT2661_INT_SOURCE_CSR);
1125 r2 = RT2661_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1127 RT2661_GUNLOCK(sc);
1132 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1133 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1136 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1137 RT2661_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1142 rt2661_tx_dma_intr(sc, &sc->mgtq);
1148 sc->sc_rx_pend = 1;
1149 (void) ddi_intr_trigger_softint(sc->sc_softintr_hdl, NULL);
1155 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1161 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1167 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1173 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1179 rt2661_tx_intr(sc);
1185 rt2661_mcu_cmd_intr(sc);
1191 rt2661_mcu_wakeup(sc);
1195 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1196 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1198 RT2661_GUNLOCK(sc);
1208 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
1217 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
1218 rssi += sc->rssi_2ghz_corr;
1227 rssi += sc->rssi_5ghz_corr;
1346 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1349 struct ieee80211com *ic = &sc->sc_ic;
1406 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1419 mutex_enter(&sc->sc_txlock);
1420 ring = &sc->txq[0];
1424 sc->sc_need_sched = 1;
1425 sc->sc_tx_nobuf++;
1449 sc->sc_tx_err++;
1459 sc->sc_tx_err++;
1490 rt2661_ack_rate(ic, rate), ic->ic_flags) + sc->sifs;
1495 rt2661_setup_tx_desc(sc, desc, flags, 0, pktlen, rate, 0);
1513 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << 0);
1524 mutex_exit(&sc->sc_txlock);
1532 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1545 if ((!RT2661_IS_RUNNING(sc)) || RT2661_IS_SUSPEND(sc)) {
1550 ring = &sc->mgtq;
1554 sc->sc_tx_nobuf++;
1578 sc->sc_tx_err++;
1586 sc->sc_tx_err++;
1607 rate, ic->ic_flags) + sc->sifs;
1618 rt2661_setup_tx_desc(sc, desc, flags, 0, pktlen, rate, RT2661_QID_MGT);
1636 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1728 rt2661_update_promisc(struct rt2661_softc *sc)
1732 tmp = RT2661_READ(sc, RT2661_TXRX_CSR0);
1735 if (!(sc->sc_rcr & RT2661_RCR_PROMISC))
1738 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1741 (sc->sc_rcr & RT2661_RCR_PROMISC) ? "entering" : "leaving");
1747 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1753 tmp = RT2661_READ(sc, RT2661_MAC_CSR9);
1755 RT2661_WRITE(sc, RT2661_MAC_CSR9, tmp);
1762 rt2661_set_slottime(struct rt2661_softc *sc)
1764 struct ieee80211com *ic = &sc->sc_ic;
1770 tmp = RT2661_READ(sc, RT2661_MAC_CSR9);
1772 RT2661_WRITE(sc, RT2661_MAC_CSR9, tmp);
1784 rt2661_enable_mrr(struct rt2661_softc *sc)
1786 struct ieee80211com *ic = &sc->sc_ic;
1789 tmp = RT2661_READ(sc, RT2661_TXRX_CSR4);
1796 RT2661_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1800 rt2661_set_txpreamble(struct rt2661_softc *sc)
1804 tmp = RT2661_READ(sc, RT2661_TXRX_CSR4);
1807 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
1810 RT2661_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1814 rt2661_set_basicrates(struct rt2661_softc *sc)
1816 struct ieee80211com *ic = &sc->sc_ic;
1821 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0x3);
1824 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0x150);
1827 RT2661_WRITE(sc, RT2661_TXRX_CSR5, 0xf);
1832 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
1837 RT2661_WRITE(sc, RT2661_MAC_CSR4, tmp);
1840 RT2661_WRITE(sc, RT2661_MAC_CSR5, tmp);
1848 rt2661_enable_tsf_sync(struct rt2661_softc *sc)
1850 struct ieee80211com *ic = &sc->sc_ic;
1853 tmp = RT2661_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
1862 RT2661_WRITE(sc, RT2661_TXRX_CSR9, tmp);
1869 struct rt2661_softc *sc = arg;
1870 struct ieee80211com *ic = &sc->sc_ic;
1879 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1882 rt2661_amrr_node_init(&sc->amrr, &((struct rt2661_node *)ni)->amn);
1895 struct rt2661_softc *sc = arg;
1898 rt2661_amrr_choose(&sc->amrr, ni, &rn->amn);
1908 rt2661_rx_tune(struct rt2661_softc *sc)
1919 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
1921 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
1922 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
1926 dbm = sc->avg_rssi;
1928 cca = RT2661_READ(sc, RT2661_STA_CSR1) & 0xffff;
1935 bbp17 = sc->bbp17; /* current value */
1958 if (bbp17 != sc->bbp17) {
1960 "BBP17 %x->%x\n", sc->bbp17, bbp17);
1961 rt2661_bbp_write(sc, 17, bbp17);
1962 sc->bbp17 = bbp17;
1973 struct rt2661_softc *sc = arg;
1974 struct ieee80211com *ic = &sc->sc_ic;
1977 rt2661_iter_func(sc, ic->ic_bss);
1982 if (++sc->ncalls & 1)
1983 rt2661_rx_tune(sc);
1985 sc->sc_rssadapt_id = timeout(rt2661_updatestats, (void *)sc,
1992 struct rt2661_softc *sc = (struct rt2661_softc *)ic;
1998 RT2661_GLOCK(sc);
2001 sc->sc_ostate = ostate;
2006 if (sc->sc_scan_id != 0) {
2007 (void) untimeout(sc->sc_scan_id);
2008 sc->sc_scan_id = 0;
2011 if (sc->sc_rssadapt_id) {
2012 (void) untimeout(sc->sc_rssadapt_id);
2013 sc->sc_rssadapt_id = 0;
2020 tmp = RT2661_READ(sc, RT2661_TXRX_CSR9);
2021 RT2661_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
2025 rt2661_set_chan(sc, ic->ic_curchan);
2026 sc->sc_scan_id = timeout(rt2661_next_scan, (void *)sc,
2031 rt2661_set_chan(sc, ic->ic_curchan);
2034 rt2661_set_chan(sc, ic->ic_curchan);
2038 rt2661_set_slottime(sc);
2039 rt2661_enable_mrr(sc);
2040 rt2661_set_txpreamble(sc);
2041 rt2661_set_basicrates(sc);
2042 rt2661_set_bssid(sc, ni->in_bssid);
2051 sc->ncalls = 0;
2052 sc->avg_rssi = -95; /* reset EMA */
2053 sc->sc_rssadapt_id = timeout(rt2661_updatestats,
2054 (void *)sc, drv_usectohz(200 * 1000));
2055 rt2661_enable_tsf_sync(sc);
2062 RT2661_GUNLOCK(sc);
2064 err = sc->sc_newstate(ic, nstate, arg);
2090 rt2661_stop_locked(struct rt2661_softc *sc)
2094 if (RT2661_IS_RUNNING(sc)) {
2095 sc->sc_tx_timer = 0;
2098 RT2661_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2101 tmp = RT2661_READ(sc, RT2661_TXRX_CSR0);
2102 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2105 RT2661_WRITE(sc, RT2661_MAC_CSR1, 3);
2106 RT2661_WRITE(sc, RT2661_MAC_CSR1, 0);
2109 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
2110 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2113 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2114 RT2661_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2117 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2118 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2119 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2120 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2121 rt2661_reset_tx_ring(sc, &sc->mgtq);
2122 rt2661_reset_rx_ring(sc, &sc->rxq);
2127 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
2132 RT2661_WRITE(sc, RT2661_MAC_CSR2, tmp);
2135 RT2661_WRITE(sc, RT2661_MAC_CSR3, tmp);
2139 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
2145 if (!(RT2661_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
2156 RT2661_WRITE(sc, RT2661_PHY_CSR3, val);
2159 val = RT2661_READ(sc, RT2661_PHY_CSR3);
2171 rt2661_bbp_init(struct rt2661_softc *sc)
2180 val = rt2661_bbp_read(sc, 0);
2193 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2199 if (sc->bbp_prom[i].reg == 0)
2201 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2209 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
2215 if (!(RT2661_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
2226 RT2661_WRITE(sc, RT2661_PHY_CSR3, tmp);
2237 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
2249 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2250 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2254 sc->bbp17 = bbp17;
2255 rt2661_bbp_write(sc, 17, bbp17);
2256 rt2661_bbp_write(sc, 96, bbp96);
2257 rt2661_bbp_write(sc, 104, bbp104);
2259 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2260 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2261 rt2661_bbp_write(sc, 75, 0x80);
2262 rt2661_bbp_write(sc, 86, 0x80);
2263 rt2661_bbp_write(sc, 88, 0x80);
2266 rt2661_bbp_write(sc, 35, bbp35);
2267 rt2661_bbp_write(sc, 97, bbp97);
2268 rt2661_bbp_write(sc, 98, bbp98);
2270 tmp = RT2661_READ(sc, RT2661_PHY_CSR0);
2276 RT2661_WRITE(sc, RT2661_PHY_CSR0, tmp);
2279 sc->sifs = IEEE80211_IS_CHAN_5GHZ(c) ? 16 : 10;
2283 rt2661_select_antenna(struct rt2661_softc *sc)
2288 bbp4 = rt2661_bbp_read(sc, 4);
2289 bbp77 = rt2661_bbp_read(sc, 77);
2294 tmp = RT2661_READ(sc, RT2661_TXRX_CSR0);
2295 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2297 rt2661_bbp_write(sc, 4, bbp4);
2298 rt2661_bbp_write(sc, 77, bbp77);
2301 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2305 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
2311 if (!(RT2661_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
2323 RT2661_WRITE(sc, RT2661_PHY_CSR4, tmp);
2325 /* remember last written value in sc */
2326 sc->rf_regs[reg] = val;
2333 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
2335 struct ieee80211com *ic = &sc->sc_ic;
2346 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
2353 power = sc->txpow[i];
2366 if (ic->ic_flags != sc->sc_curchan->ich_flags) {
2367 rt2661_select_band(sc, c);
2368 rt2661_select_antenna(sc);
2370 sc->sc_curchan = c;
2372 rt2661_rf_write(sc, RT2661_RF1, rfprog[i].r1);
2373 rt2661_rf_write(sc, RT2661_RF2, rfprog[i].r2);
2374 rt2661_rf_write(sc, RT2661_RF3, rfprog[i].r3 | power << 7);
2375 rt2661_rf_write(sc, RT2661_RF4, rfprog[i].r4 | sc->rffreq << 10);
2379 rt2661_rf_write(sc, RT2661_RF1, rfprog[i].r1);
2380 rt2661_rf_write(sc, RT2661_RF2, rfprog[i].r2);
2381 rt2661_rf_write(sc, RT2661_RF3, rfprog[i].r3 | power << 7 | 1);
2382 rt2661_rf_write(sc, RT2661_RF4, rfprog[i].r4 | sc->rffreq << 10);
2386 rt2661_rf_write(sc, RT2661_RF1, rfprog[i].r1);
2387 rt2661_rf_write(sc, RT2661_RF2, rfprog[i].r2);
2388 rt2661_rf_write(sc, RT2661_RF3, rfprog[i].r3 | power << 7);
2389 rt2661_rf_write(sc, RT2661_RF4, rfprog[i].r4 | sc->rffreq << 10);
2392 bbp3 = rt2661_bbp_read(sc, 3);
2395 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
2398 rt2661_bbp_write(sc, 3, bbp3);
2401 rt2661_bbp_write(sc, 94, bbp94);
2409 rt2661_init(struct rt2661_softc *sc)
2413 struct ieee80211com *ic = &sc->sc_ic;
2417 RT2661_GLOCK(sc);
2419 rt2661_stop_locked(sc);
2421 if (!RT2661_IS_FWLOADED(sc)) {
2422 err = rt2661_load_microcode(sc, ucode, usize);
2428 sc->sc_flags |= RT2661_F_FWLOADED;
2432 RT2661_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].paddr);
2433 RT2661_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].paddr);
2434 RT2661_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].paddr);
2435 RT2661_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].paddr);
2438 RT2661_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.paddr);
2441 RT2661_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.paddr);
2444 RT2661_WRITE(sc, RT2661_TX_RING_CSR0,
2450 RT2661_WRITE(sc, RT2661_TX_RING_CSR1,
2456 RT2661_WRITE(sc, RT2661_RX_RING_CSR,
2462 RT2661_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2465 RT2661_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2468 RT2661_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2472 RT2661_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2474 rt2661_set_macaddr(sc, ic->ic_macaddr);
2477 RT2661_WRITE(sc, RT2661_MAC_CSR1, 3);
2478 RT2661_WRITE(sc, RT2661_MAC_CSR1, 0);
2482 if (RT2661_READ(sc, RT2661_MAC_CSR12) & 8)
2489 rt2661_stop_locked(sc);
2490 RT2661_GUNLOCK(sc);
2494 if (rt2661_bbp_init(sc) != RT2661_SUCCESS) {
2495 rt2661_stop_locked(sc);
2496 RT2661_GUNLOCK(sc);
2501 sc->sc_curchan = ic->ic_bss->in_chan = ic->ic_curchan;
2502 rt2661_select_band(sc, sc->sc_curchan);
2503 rt2661_select_antenna(sc);
2504 rt2661_set_chan(sc, sc->sc_curchan);
2507 tmp = RT2661_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2515 if (!(sc->sc_rcr & RT2661_RCR_PROMISC))
2519 RT2661_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2525 *fptr = RT2661_MEM_READ1(sc, off++);
2529 RT2661_WRITE(sc, RT2661_MAC_CSR1, 4);
2532 RT2661_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2535 RT2661_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2536 RT2661_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2539 RT2661_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2540 RT2661_GUNLOCK(sc);
2547 rt2661_stop(struct rt2661_softc *sc)
2549 if (!RT2661_IS_FASTREBOOT(sc))
2550 RT2661_GLOCK(sc);
2551 rt2661_stop_locked(sc);
2552 if (!RT2661_IS_FASTREBOOT(sc))
2553 RT2661_GUNLOCK(sc);
2559 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2560 struct ieee80211com *ic = &sc->sc_ic;
2563 err = rt2661_init(sc);
2572 RT2661_GLOCK(sc);
2573 sc->sc_flags |= RT2661_F_RUNNING;
2574 RT2661_GUNLOCK(sc);
2578 rt2661_stop(sc);
2585 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2587 (void) rt2661_stop(sc);
2589 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2591 RT2661_GLOCK(sc);
2592 sc->sc_flags &= ~RT2661_F_RUNNING;
2593 RT2661_GUNLOCK(sc);
2599 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2600 struct ieee80211com *ic = &sc->sc_ic;
2604 RT2661_GLOCK(sc);
2607 if (RT2661_IS_RUNNING(sc)) {
2608 RT2661_GUNLOCK(sc);
2609 (void) rt2661_init(sc);
2612 RT2661_GLOCK(sc);
2616 RT2661_GUNLOCK(sc);
2626 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2629 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2639 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2641 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, mph);
2648 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2649 ieee80211com_t *ic = &sc->sc_ic;
2654 RT2661_GLOCK(sc);
2657 if (RT2661_IS_RUNNING(sc)) {
2658 RT2661_GUNLOCK(sc);
2659 (void) rt2661_init(sc);
2662 RT2661_GLOCK(sc);
2667 RT2661_GUNLOCK(sc);
2674 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2675 struct ieee80211com *ic = &sc->sc_ic;
2678 if (RT2661_IS_SUSPEND(sc)) {
2726 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2729 sc->sc_rcr |= RT2661_RCR_PROMISC;
2730 sc->sc_rcr |= RT2661_RCR_MULTI;
2732 sc->sc_rcr &= ~RT2661_RCR_PROMISC;
2733 sc->sc_rcr &= ~RT2661_RCR_MULTI;
2736 rt2661_update_promisc(sc);
2743 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
2744 struct ieee80211com *ic = &sc->sc_ic;
2748 RT2661_GLOCK(sc);
2756 *val = sc->sc_tx_nobuf;
2759 *val = sc->sc_rx_nobuf;
2762 *val = sc->sc_rx_err;
2778 *val = sc->sc_tx_err;
2781 *val = sc->sc_tx_retries;
2793 RT2661_GUNLOCK(sc);
2796 RT2661_GUNLOCK(sc);
2799 RT2661_GUNLOCK(sc);
2807 struct rt2661_softc *sc;
2824 sc = ddi_get_soft_state(rt2661_soft_state_p,
2826 ASSERT(sc != NULL);
2827 RT2661_GLOCK(sc);
2828 sc->sc_flags &= ~RT2661_F_SUSPEND;
2829 RT2661_GUNLOCK(sc);
2830 if (RT2661_IS_RUNNING(sc))
2831 (void) rt2661_init(sc);
2848 sc = ddi_get_soft_state(rt2661_soft_state_p, instance);
2849 ic = (struct ieee80211com *)&sc->sc_ic;
2850 sc->sc_dev = devinfo;
2853 err = ddi_regs_map_setup(devinfo, 0, &sc->sc_cfg_base, 0, 0,
2854 &rt2661_csr_accattr, &sc->sc_cfg_handle);
2861 cachelsz = ddi_get8(sc->sc_cfg_handle,
2862 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
2865 sc->sc_cachelsz = cachelsz << 2;
2866 sc->sc_dmabuf_size = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
2868 vendor_id = ddi_get16(sc->sc_cfg_handle,
2869 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_VENID));
2870 device_id = ddi_get16(sc->sc_cfg_handle,
2871 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_DEVID));
2881 ddi_put16(sc->sc_cfg_handle,
2882 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM),
2884 ddi_put8(sc->sc_cfg_handle,
2885 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8);
2886 ddi_put8(sc->sc_cfg_handle,
2887 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10);
2891 &sc->sc_io_base, 0, 0, &rt2661_csr_accattr, &sc->sc_io_handle);
2914 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
2916 err = ddi_intr_alloc(devinfo, sc->sc_intr_htable,
2924 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
2931 sc->amrr.amrr_min_success_threshold = 1;
2932 sc->amrr.amrr_max_success_threshold = 15;
2936 if ((val = RT2661_READ(sc, RT2661_MAC_CSR0)) != 0)
2947 rt2661_read_eeprom(sc);
2952 rt2661_get_rf(sc->rf_rev),
2974 err = rt2661_load_microcode(sc, ucode, usize);
2981 sc->sc_flags = 0;
2982 sc->sc_flags |= RT2661_F_FWLOADED;
2988 err = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
2997 err = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
3004 err = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
3011 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
3012 mutex_init(&sc->sc_txlock, NULL, MUTEX_DRIVER, NULL);
3013 mutex_init(&sc->sc_rxlock, NULL, MUTEX_DRIVER, NULL);
3055 sc->sc_newstate = ic->ic_newstate;
3060 err = ddi_intr_add_softint(devinfo, &sc->sc_softintr_hdl,
3061 DDI_INTR_SOFTPRI_MAX, rt2661_softintr, (caddr_t)sc);
3068 err = ddi_intr_add_handler(sc->sc_intr_htable[0], rt2661_intr,
3069 (caddr_t)sc, NULL);
3076 err = ddi_intr_enable(sc->sc_intr_htable[0]);
3098 macp->m_driver = sc;
3133 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
3135 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
3137 (void) ddi_intr_remove_softint(sc->sc_softintr_hdl);
3138 sc->sc_softintr_hdl = NULL;
3140 mutex_destroy(&sc->sc_genlock);
3141 mutex_destroy(&sc->sc_txlock);
3142 mutex_destroy(&sc->sc_rxlock);
3144 rt2661_free_rx_ring(sc, &sc->rxq);
3146 rt2661_free_tx_ring(sc, &sc->mgtq);
3149 rt2661_free_tx_ring(sc, &sc->txq[ac]);
3151 (void) ddi_intr_free(sc->sc_intr_htable[0]);
3153 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
3155 ddi_regs_map_free(&sc->sc_io_handle);
3157 ddi_regs_map_free(&sc->sc_cfg_handle);
3166 struct rt2661_softc *sc;
3168 sc = ddi_get_soft_state(rt2661_soft_state_p, ddi_get_instance(devinfo));
3174 if (RT2661_IS_RUNNING(sc))
3175 rt2661_stop(sc);
3176 RT2661_GLOCK(sc);
3177 sc->sc_flags |= RT2661_F_SUSPEND;
3178 sc->sc_flags &= ~RT2661_F_FWLOADED;
3179 RT2661_GUNLOCK(sc);
3187 if (mac_disable(sc->sc_ic.ic_mach) != 0)
3193 (void) mac_unregister(sc->sc_ic.ic_mach);
3195 (void) ddi_intr_remove_softint(sc->sc_softintr_hdl);
3196 sc->sc_softintr_hdl = NULL;
3197 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
3198 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
3199 (void) ddi_intr_free(sc->sc_intr_htable[0]);
3200 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
3205 ieee80211_detach(&sc->sc_ic);
3207 mutex_destroy(&sc->sc_genlock);
3208 mutex_destroy(&sc->sc_txlock);
3209 mutex_destroy(&sc->sc_rxlock);
3211 rt2661_free_tx_ring(sc, &sc->txq[0]);
3212 rt2661_free_tx_ring(sc, &sc->txq[1]);
3213 rt2661_free_tx_ring(sc, &sc->txq[2]);
3214 rt2661_free_tx_ring(sc, &sc->txq[3]);
3215 rt2661_free_tx_ring(sc, &sc->mgtq);
3216 rt2661_free_rx_ring(sc, &sc->rxq);
3218 ddi_regs_map_free(&sc->sc_io_handle);
3219 ddi_regs_map_free(&sc->sc_cfg_handle);
3232 struct rt2661_softc *sc;
3234 sc = ddi_get_soft_state(rt2661_soft_state_p, ddi_get_instance(dip));
3235 if (sc == NULL)
3245 sc->sc_flags |= RT2661_F_QUIESCE;
3250 rt2661_stop(sc);