Lines Matching refs:reg1
1275 * Complete outstanding read and/or write ops on [reg0, reg1]
1276 * ([reg1, reg0]) before starting new ops on the same region. See
1279 #define RTW_BARRIER(regs, reg0, reg1, flags)
1283 * MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags)
1291 #define RTW_SYNC(regs, reg0, reg1) \
1292 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
1297 #define RTW_WBW(regs, reg0, reg1) \
1298 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
1303 #define RTW_WBR(regs, reg0, reg1) \
1304 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
1309 #define RTW_RBR(regs, reg0, reg1) \
1310 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
1315 #define RTW_RBW(regs, reg0, reg1) \
1316 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
1318 #define RTW_WBRW(regs, reg0, reg1) \
1319 RTW_BARRIER(regs, reg0, reg1, \