47  * nth bit, BIT(0) == 0x1.
49 #define	BIT(n) (((n) == 32) ? 0 : ((uint32_t)1 << (n)))
54 #define	BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
136 #define	RTW_BRSR_BPLCP	BIT(8)
146 #define	RTW_BRSR_MBR8181_1MBPS	BIT(0)
147 #define	RTW_BRSR_MBR8181_2MBPS	BIT(1)
148 #define	RTW_BRSR_MBR8181_5MBPS	BIT(2)
149 #define	RTW_BRSR_MBR8181_11MBPS	BIT(3)
170 #define	RTW_CR_RST	BIT(4)
177 #define	RTW_CR_RE	BIT(3)
184 #define	RTW_CR_TE	BIT(2)
190 #define	RTW_CR_MULRW	BIT(0)
195 #define	RTW_INTR_TXFOVW	BIT(15)		/* Tx FIFO Overflow */
199 #define	RTW_INTR_TIMEOUT	BIT(14)
205 #define	RTW_INTR_BCNINT	BIT(13)
211 #define	RTW_INTR_ATIMINT	BIT(12)
217 #define	RTW_INTR_TBDER	BIT(11)
218 #define	RTW_INTR_TBDOK	BIT(10)	/* Tx Beacon Descriptor OK */
223 #define	RTW_INTR_THPDER	BIT(9)
224 #define	RTW_INTR_THPDOK	BIT(8)	/* Tx High Priority Descriptor OK */
229 #define	RTW_INTR_TNPDER	BIT(7)
230 #define	RTW_INTR_TNPDOK	BIT(6)	/* Tx Normal Priority Descriptor OK */
235 #define	RTW_INTR_RXFOVW	BIT(5)
236 #define	RTW_INTR_RDU	BIT(4)	/* Rx Descriptor Unavailable */
241 #define	RTW_INTR_TLPDER	BIT(3)
242 #define	RTW_INTR_TLPDOK	BIT(2)	/* Tx Low Priority Descriptor OK */
243 #define	RTW_INTR_RER	BIT(1)	/* Rx Error: CRC32 or ICV error */
244 #define	RTW_INTR_ROK	BIT(0)	/* Rx OK */
258 #define	RTW_TCR_CWMIN	BIT(31)	/* 1: CWmin = 8, 0: CWmin = 32. */
263 #define	RTW_TCR_SWSEQ	BIT(30)
275 #define	RTW_TCR_SAT	BIT(24)
287 #define	RTW_TCR_DISCW		BIT(20)	/* disable 802.11 random backoff */
292 #define	RTW_TCR_ICV		BIT(19)
310 #define	RTW_TCR_CRC	BIT(16)
318 #define	RTW_RCR_ONLYERLPKT	BIT(31)
319 #define	RTW_RCR_ENCS2		BIT(30)	/* enable carrier sense method 2 */
320 #define	RTW_RCR_ENCS1		BIT(29)	/* enable carrier sense method 1 */
321 #define	RTW_RCR_ENMARP		BIT(28)	/* enable MAC auto-reset PHY */
327 #define	RTW_RCR_CBSSID		BIT(23)
328 #define	RTW_RCR_APWRMGT		BIT(22)	/* accept packets w/ PWRMGMT bit set */
333 #define	RTW_RCR_ADD3		BIT(21)
334 #define	RTW_RCR_AMF		BIT(20)	/* accept management frames */
335 #define	RTW_RCR_ACF		BIT(19)	/* accept control frames */
336 #define	RTW_RCR_ADF		BIT(18)	/* accept data frames */
349 #define	RTW_RCR_AICV		BIT(12)	/* accept frames w/ ICV errors */
367 #define	RTW_RCR_9356SEL		BIT(6)
369 #define	RTW_RCR_ACRC32		BIT(5)	/* accept frames w/ CRC32 errors */
370 #define	RTW_RCR_AB		BIT(3)	/* accept broadcast frames */
371 #define	RTW_RCR_AM		BIT(2)	/* accept multicast frames */
375 #define	RTW_RCR_APM		BIT(1)
376 #define	RTW_RCR_AAP		BIT(0)	/* accept frames w/ destination */
450 #define	RTW_9346CR_EECS	BIT(3)
451 #define	RTW_9346CR_EESK	BIT(2)
452 #define	RTW_9346CR_EEDI	BIT(1)
453 #define	RTW_9346CR_EEDO	BIT(0)	/* read-only */
459 #define	RTW_CONFIG0_WEP40	BIT(7)
463 #define	RTW_CONFIG0_WEP104	BIT(6)
469 #define	RTW_CONFIG0_LEDGPOEN	BIT(4)
473 #define	RTW_CONFIG0_AUXPWR	BIT(3)
516 #define	RTW_CONFIG1_LWACT	BIT(4)
518 #define	RTW_CONFIG1_MEMMAP	BIT(3)	/* using PCI memory space, read-only */
519 #define	RTW_CONFIG1_IOMAP	BIT(2)	/* using PCI I/O space, read-only */
524 #define	RTW_CONFIG1_VPD		BIT(1)
525 #define	RTW_CONFIG1_PMEN	BIT(0)	/* Power Management Enable: TBD */
532 #define	RTW_CONFIG2_LCK	BIT(7)
533 #define	RTW_CONFIG2_ANT	BIT(6)	/* diversity enabled, read-only */
537 #define	RTW_CONFIG2_DPS	BIT(3)
538 #define	RTW_CONFIG2_PAPESIGN		BIT(2)		/* TBD, from EEPROM */
554 #define	RTW_ANAPARM_TXDACOFF	BIT(27)
641 #define	RTW_CONFIG3_GNTSEL	BIT(7)	/* Grant Select, read-only */
646 #define	RTW_CONFIG3_PARMEN	BIT(6)
651 #define	RTW_CONFIG3_MAGIC	BIT(5)
656 #define	RTW_CONFIG3_CARDBEN	BIT(3)
660 #define	RTW_CONFIG3_CLKRUNEN	BIT(2)
664 #define	RTW_CONFIG3_FUNCREGEN	BIT(1)
668 #define	RTW_CONFIG3_FBTBEN	BIT(0)
677 #define	RTW_CONFIG4_VCOPDN	BIT(7)
688 #define	RTW_CONFIG4_PWROFF	BIT(6)
695 #define	RTW_CONFIG4_PWRMGT	BIT(5)
705 #define	RTW_CONFIG4_LWPME	BIT(4)
709 #define	RTW_CONFIG4_LWPTN	BIT(2)
721 #define	RTW_PSR_GPO	BIT(7)	/* Control/status of pin 52. */
722 #define	RTW_PSR_GPI	BIT(6)	/* Status of pin 64. */
726 #define	RTW_PSR_LEDGPO1	BIT(5)
730 #define	RTW_PSR_LEDGPO0	BIT(4)
731 #define	RTW_PSR_UWF	BIT(1)	/* Enable Unicast Wakeup Frame */
732 #define	RTW_PSR_PSEN	BIT(0)	/* 1: page 1, 0: page 0 */
742 #define	RTW_SCR_TXSECON		BIT(1)
747 #define	RTW_SCR_RXSECON		BIT(0)
777 #define	RTW_PHYDELAY_REVC_MAGIC	BIT(3)
793 #define	RTW_BB_WREN		BIT(7)		/* write enable */
804 #define	RTW_PHYCFG_MAC_POLL	BIT(31)
809 #define	RTW_PHYCFG_HST		BIT(30)
820 #define	RTW_PHYCFG_HST_EN		BIT(2)
821 #define	RTW_PHYCFG_HST_CLK		BIT(1)
822 #define	RTW_PHYCFG_HST_DATA		BIT(0)
877 #define	RTW_CONFIG5_TXFIFOOK	BIT(7)	/* Tx FIFO self-test pass, read-only */
878 #define	RTW_CONFIG5_RXFIFOOK	BIT(6)	/* Rx FIFO self-test pass, read-only */
883 #define	RTW_CONFIG5_CALON	BIT(5)
884 #define	RTW_CONFIG5_EACPI	BIT(2)	/* Enable ACPI Wake up, default 0 */
888 #define	RTW_CONFIG5_LANWAKE	BIT(1)
895 #define	RTW_CONFIG5_PMESTS	BIT(0)
905 #define	RTW_TPPOLL_BQ	BIT(7)
910 #define	RTW_TPPOLL_HPQ	BIT(6)
919 #define	RTW_TPPOLL_NPQ	BIT(5)
924 #define	RTW_TPPOLL_LPQ	BIT(4)
929 #define	RTW_TPPOLL_SBQ	BIT(3)
933 #define	RTW_TPPOLL_SHPQ	BIT(2)
938 #define	RTW_TPPOLL_SNPQ	BIT(1)
942 #define	RTW_TPPOLL_SLPQ	BIT(0)
980 #define	RTW_FER_INTR	BIT(15)	/* set when RTW_FFER_INTR is set */
981 #define	RTW_FER_GWAKE	BIT(4)	/* General Wakeup */
987 #define	RTW_FEMR_INTR	BIT(15)	/* set when RTW_FFER_INTR is set */
988 #define	RTW_FEMR_WKUP	BIT(14)	/* Wakeup Mask */
989 #define	RTW_FEMR_GWAKE	BIT(4)	/* General Wakeup */
996 #define	RTW_FPSR_INTR	BIT(15)	/* TBD */
997 #define	RTW_FPSR_GWAKE	BIT(4)	/* General Wakeup: TBD */
1004 #define	RTW_FFER_INTR	BIT(15)	/* TBD */
1005 #define	RTW_FFER_GWAKE	BIT(4)	/* General Wakeup: TBD */
1047 #define	RTW_SR_RFPARM_DIGPHY	BIT(0)		/* 1: digital PHY */
1048 #define	RTW_SR_RFPARM_DFLANTB	BIT(1)		/* 1: antenna B is default */
1078 #define	RTW_TXCTL0_OWN			BIT(31)		/* 1: ready to Tx */
1079 #define	RTW_TXCTL0_RSVD0		BIT(30)		/* reserved */
1080 #define	RTW_TXCTL0_FS			BIT(29)		/* first segment */
1081 #define	RTW_TXCTL0_LS			BIT(28)		/* last segment */
1089 #define	RTW_TXCTL0_RTSEN		BIT(23)		/* RTS Enable */
1097 #define	RTW_TXCTL0_BEACON		BIT(18)	/* packet is a beacon */
1098 #define	RTW_TXCTL0_MOREFRAG		BIT(17)	/* another fragment follows */
1102 #define	RTW_TXCTL0_SPLCP		BIT(16)
1115 #define	RTW_TXSTAT_TOK		BIT(15)
1122 #define	RTW_TXCTL1_LENGEXT	BIT(31)
1146 #define	RTW_RXCTL_OWN		BIT(31)		/* 1: owned by NIC */
1147 #define	RTW_RXCTL_EOR		BIT(30)		/* end of ring */
1148 #define	RTW_RXCTL_FS		BIT(29)		/* first segment */
1149 #define	RTW_RXCTL_LS		BIT(28)		/* last segment */
1157 #define	RTW_RXSTAT_DMAFAIL	BIT(27)		/* DMA failure on this pkt */
1161 #define	RTW_RXSTAT_BOVF		BIT(26)
1165 #define	RTW_RXSTAT_SPLCP	BIT(25)
1166 #define	RTW_RXSTAT_RSVD1	BIT(24)		/* reserved */
1172 #define	RTW_RXSTAT_MIC		BIT(19)		/* XXX from reference driver */
1173 #define	RTW_RXSTAT_MAR		BIT(18)		/* is multicast */
1174 #define	RTW_RXSTAT_PAR		BIT(17)		/* matches RTL8180's MAC */
1175 #define	RTW_RXSTAT_BAR		BIT(16)		/* is broadcast */
1180 #define	RTW_RXSTAT_RES		BIT(15)
1181 #define	RTW_RXSTAT_PWRMGT	BIT(14)		/* 802.11 PWRMGMT bit is set */
1185 #define	RTW_RXSTAT_CRC16	BIT(14)
1186 #define	RTW_RXSTAT_CRC32	BIT(13)		/* CRC32 error */
1187 #define	RTW_RXSTAT_ICV		BIT(12)		/* ICV error */
1216 #define	RTW_RXRSSI_IMR_LNA	BIT(8)		/* 1: LNA activated */

Indexes created Tue Jul 24 14:28:13 CEST 2018