Lines Matching defs:rgep
28 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg)))
29 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg)))
30 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg)))
31 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset)))
52 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno);
56 rge_reg_get32(rge_t *rgep, uintptr_t regno)
59 (void *)rgep, regno));
61 return (ddi_get32(rgep->io_handle, REG32(rgep, regno)));
64 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data);
68 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data)
71 (void *)rgep, regno, data));
73 ddi_put32(rgep->io_handle, REG32(rgep, regno), data);
76 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits);
80 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits)
85 (void *)rgep, regno, bits));
87 regval = rge_reg_get32(rgep, regno);
89 rge_reg_put32(rgep, regno, regval);
92 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits);
96 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits)
101 (void *)rgep, regno, bits));
103 regval = rge_reg_get32(rgep, regno);
105 rge_reg_put32(rgep, regno, regval);
108 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno);
112 rge_reg_get16(rge_t *rgep, uintptr_t regno)
115 (void *)rgep, regno));
117 return (ddi_get16(rgep->io_handle, REG16(rgep, regno)));
120 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data);
124 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data)
127 (void *)rgep, regno, data));
129 ddi_put16(rgep->io_handle, REG16(rgep, regno), data);
132 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno);
136 rge_reg_get8(rge_t *rgep, uintptr_t regno)
139 (void *)rgep, regno));
141 return (ddi_get8(rgep->io_handle, REG8(rgep, regno)));
144 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data);
148 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data)
151 (void *)rgep, regno, data));
153 ddi_put8(rgep->io_handle, REG8(rgep, regno), data);
156 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits);
160 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits)
165 (void *)rgep, regno, bits));
167 regval = rge_reg_get8(rgep, regno);
169 rge_reg_put8(rgep, regno, regval);
172 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits);
176 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits)
181 (void *)rgep, regno, bits));
183 regval = rge_reg_get8(rgep, regno);
185 rge_reg_put8(rgep, regno, regval);
188 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii);
192 rge_mii_get16(rge_t *rgep, uintptr_t mii)
199 rge_reg_put32(rgep, PHY_ACCESS_REG, regval);
206 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG);
211 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32));
215 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data);
219 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data)
228 rge_reg_put32(rgep, PHY_ACCESS_REG, regval);
235 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG);
239 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail",
243 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data);
247 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data)
256 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval);
263 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG);
267 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail",
299 rge_phydump(rge_t *rgep)
304 ASSERT(mutex_owned(rgep->genlock));
307 regs[i] = rge_mii_get16(rgep, i);
320 rge_phy_check(rge_t *rgep)
324 if (rgep->param_link_up == LINK_STATE_DOWN) {
329 if (rgep->chipid.phy_ver == PHY_VER_S) {
330 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL);
332 rgep->link_down_count++;
333 if (rgep->link_down_count > 15) {
334 (void) rge_phy_reset(rgep);
335 rgep->stats.phy_reset++;
336 rgep->link_down_count = 0;
341 rgep->link_down_count = 0;
352 rge_phy_reset(rge_t *rgep)
360 control = rge_mii_get16(rgep, MII_CONTROL);
361 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET);
364 control = rge_mii_get16(rgep, MII_CONTROL);
369 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control));
387 rge_phy_update(rge_t *rgep)
403 ASSERT(mutex_owned(rgep->genlock));
410 rgep->param_adv_autoneg,
411 rgep->param_adv_pause, rgep->param_adv_asym_pause,
412 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx,
413 rgep->param_adv_100fdx, rgep->param_adv_100hdx,
414 rgep->param_adv_10fdx, rgep->param_adv_10hdx));
427 switch (rgep->param_loop_mode) {
430 adv_autoneg = rgep->param_adv_autoneg;
431 adv_pause = rgep->param_adv_pause;
432 adv_asym_pause = rgep->param_adv_asym_pause;
433 adv_1000fdx = rgep->param_adv_1000fdx;
434 adv_1000hdx = rgep->param_adv_1000hdx;
435 adv_100fdx = rgep->param_adv_100fdx;
436 adv_100hdx = rgep->param_adv_100hdx;
437 adv_10fdx = rgep->param_adv_10fdx;
438 adv_10hdx = rgep->param_adv_10hdx;
446 rgep->param_link_duplex = LINK_DUPLEX_FULL;
448 switch (rgep->param_loop_mode) {
450 if (rgep->chipid.mac_ver != MAC_VER_8101E) {
451 rgep->param_link_speed = 1000;
454 rgep->param_link_speed = 100;
461 if (rgep->chipid.mac_ver != MAC_VER_8101E) {
462 rgep->param_link_speed = 1000;
465 rgep->param_link_speed = 100;
488 if (rgep->chipid.mac_ver != MAC_VER_8101E)
529 if (rgep->chipid.is_pcie)
564 rge_phy_init(rgep);
565 if (rgep->chipid.mac_ver == MAC_VER_8168B_B ||
566 rgep->chipid.mac_ver == MAC_VER_8168B_C) {
568 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
569 rge_mii_put16(rgep, PHY_0E_REG, 0x0000);
570 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
572 rge_mii_put16(rgep, MII_AN_ADVERT, anar);
573 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl);
574 rge_mii_put16(rgep, MII_CONTROL, control);
581 void rge_phy_init(rge_t *rgep);
585 rge_phy_init(rge_t *rgep)
587 rgep->phy_mii_addr = 1;
593 switch (rgep->chipid.mac_ver) {
596 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
597 rge_mii_put16(rgep, PHY_15_REG, 0x1000);
598 rge_mii_put16(rgep, PHY_18_REG, 0x65c7);
599 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
600 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1);
601 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008);
602 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020);
603 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000);
604 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800);
605 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
606 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000);
607 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41);
608 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60);
609 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140);
610 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077);
611 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800);
612 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000);
613 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000);
614 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01);
615 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20);
616 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95);
617 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00);
618 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800);
619 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000);
620 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000);
621 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41);
622 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20);
623 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140);
624 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb);
625 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800);
626 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000);
627 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000);
628 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01);
629 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20);
630 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95);
631 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00);
632 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800);
633 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000);
634 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000);
635 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
636 rge_mii_put16(rgep, PHY_0B_REG, 0x0000);
640 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
641 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E);
642 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff);
643 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT);
644 rge_mii_put16(rgep, PHY_1F_REG, 0x0002);
645 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0);
646 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
650 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
651 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078);
652 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc);
653 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672);
654 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14);
655 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0);
656 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80);
657 rge_mii_put16(rgep, PHY_1B_REG, 0xc414);
658 rge_mii_put16(rgep, PHY_1C_REG, 0xef03);
659 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8);
660 rge_mii_put16(rgep, PHY_1F_REG, 0x0003);
661 rge_mii_put16(rgep, PHY_13_REG, 0x0600);
662 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
666 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
667 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa);
668 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173);
669 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc);
670 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0);
671 rge_mii_put16(rgep, PHY_0B_REG, 0x941a);
672 rge_mii_put16(rgep, PHY_18_REG, 0x65fe);
673 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02);
674 rge_mii_put16(rgep, PHY_1F_REG, 0x0002);
675 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e);
676 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
681 rge_mii_put16(rgep, PHY_1F_REG, 0x0001);
682 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0);
683 rge_mii_put16(rgep, PHY_1B_REG, 0xc416);
684 rge_mii_put16(rgep, PHY_1F_REG, 0x0003);
685 rge_mii_put16(rgep, PHY_12_REG, 0x6096);
686 rge_mii_put16(rgep, PHY_1F_REG, 0x0000);
691 void rge_chip_ident(rge_t *rgep);
695 rge_chip_ident(rge_t *rgep)
697 chip_id_t *chip = &rgep->chipid;
704 val32 = rge_reg_get32(rgep, TX_CONFIG_REG);
707 chip->is_pcie = pci_lcap_locate(rgep->cfg_handle,
721 val16 = rge_mii_get16(rgep, PHY_ID_REG_2);
730 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40);
733 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG);
736 rge_reg_put32(rgep, 0x7c, 0x000700ff);
738 rge_reg_put32(rgep, 0x7c, 0x0007ff00);
747 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY;
748 if (rgep->default_mtu > ETHERMTU) {
749 rge_notice(rgep, "Jumbo packets not supported "
751 rgep->default_mtu = ETHERMTU;
754 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY)
755 rgep->head_room = 0;
757 rgep->head_room = RGE_HEADROOM;
762 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU)
763 rgep->default_mtu = ETHERMTU;
764 if (rgep->default_mtu > ETHERMTU) {
765 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO;
766 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO;
767 rgep->ethmax_size = RGE_JUMBO_SIZE;
769 rgep->rxbuf_size = RGE_BUFF_SIZE_STD;
770 rgep->txbuf_size = RGE_BUFF_SIZE_STD;
771 rgep->ethmax_size = ETHERMAX;
777 rgep->tick_delta = drv_usectohz(1000*1000/CLK_TICK);
780 rgep->curr_tick = ddi_get_lbolt() - 2*rgep->tick_delta;
782 rgep->ifname, chip->mac_ver, chip->phy_ver));
794 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp);
798 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp)
803 handle = rgep->cfg_handle;
833 int rge_chip_reset(rge_t *rgep);
837 rge_chip_reset(rge_t *rgep)
845 rge_reg_clr8(rgep, RT_COMMAND_REG,
851 rgep->int_mask = INT_MASK_NONE;
852 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
857 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL);
862 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET);
869 val8 = rge_reg_get8(rgep, RT_COMMAND_REG);
871 rgep->rge_chip_state = RGE_CHIP_RESET;
875 RGE_REPORT((rgep, "rge_chip_reset fail."));
879 void rge_chip_init(rge_t *rgep);
883 rge_chip_init(rge_t *rgep)
888 chip_id_t *chip = &rgep->chipid;
896 rge_ephy_put16(rgep, 0x01, 0x1bd3);
901 val16 = rge_reg_get8(rgep, PHY_STATUS_REG);
903 rge_reg_put16(rgep, PHY_STATUS_REG, val16);
904 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01);
905 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088);
906 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000);
907 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0);
908 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068);
909 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG);
912 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32);
913 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068);
919 rgep->param_link_up = LINK_STATE_DOWN;
920 rge_phy_update(rgep);
927 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG);
931 rge_reg_put8(rgep, RESV_82_REG, 0x01);
937 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03));
943 rge_reg_set8(rgep, RT_COMMAND_REG,
949 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32;
950 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32);
951 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0);
953 val32 |= rgep->dma_area_stats.cookie.dmac_laddress;
954 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32);
959 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
964 if (rgep->default_mtu > ETHERMTU) {
965 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO);
966 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO);
967 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) {
968 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD);
969 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD);
971 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E);
972 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E);
978 val32 = rge_reg_get32(rgep, RX_CONFIG_REG);
980 if (rgep->promisc)
982 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig);
987 val32 = rge_reg_get32(rgep, TX_CONFIG_REG);
989 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig);
994 val32 = rgep->tx_desc.cookie.dmac_laddress;
995 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32);
996 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32;
997 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32);
998 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0);
999 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0);
1000 val32 = rgep->rx_desc.cookie.dmac_laddress;
1001 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32);
1002 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32;
1003 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32);
1008 if (rgep->chipid.mac_ver != MAC_VER_8101E)
1009 rge_reg_put16(rgep, RESV_E2_REG, 0x282a);
1011 rge_reg_put16(rgep, RESV_E2_REG, 0x0000);
1016 hashp = (uint32_t *)rgep->mcast_hash;
1017 if (rgep->promisc) {
1018 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U);
1019 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U);
1021 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0]));
1022 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1]));
1031 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0);
1032 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE);
1033 rge_reg_put32(rgep, TIMER_COUNT_REG, 0);
1038 rge_reg_clr8(rgep, RT_CONFIG_5_REG, RT_UNI_WAKE_FRAME);
1043 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1051 void rge_chip_start(rge_t *rgep);
1055 rge_chip_start(rge_t *rgep)
1060 bzero(&rgep->stats, sizeof (rge_stats_t));
1061 DMA_ZERO(rgep->dma_area_stats);
1066 rge_reg_set8(rgep, RT_COMMAND_REG,
1072 rgep->int_mask = RGE_INT_MASK;
1073 if (rgep->chipid.is_pcie) {
1074 rgep->int_mask |= NO_TXDESC_INT;
1076 rgep->rx_fifo_ovf = 0;
1077 rgep->int_mask |= RX_FIFO_OVERFLOW_INT;
1078 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1083 rgep->rge_chip_state = RGE_CHIP_RUNNING;
1093 void rge_chip_stop(rge_t *rgep, boolean_t fault);
1097 rge_chip_stop(rge_t *rgep, boolean_t fault)
1102 rgep->int_mask = INT_MASK_NONE;
1103 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1108 if (!rgep->suspended) {
1109 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL);
1115 rge_reg_clr8(rgep, RT_COMMAND_REG,
1119 rgep->rge_chip_state = RGE_CHIP_FAULT;
1121 rgep->rge_chip_state = RGE_CHIP_STOPPED;
1127 static void rge_get_mac_addr(rge_t *rgep);
1131 rge_get_mac_addr(rge_t *rgep)
1133 uint8_t *macaddr = rgep->netaddr;
1139 val32 = rge_reg_get32(rgep, ID_0_REG);
1151 val32 = rge_reg_get32(rgep, ID_4_REG);
1157 static void rge_set_mac_addr(rge_t *rgep);
1161 rge_set_mac_addr(rge_t *rgep)
1163 uint8_t *p = rgep->netaddr;
1169 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1185 rge_reg_put32(rgep, ID_0_REG, val32);
1197 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff;
1198 rge_reg_put32(rgep, ID_4_REG, val32);
1203 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1206 static void rge_set_multi_addr(rge_t *rgep);
1210 rge_set_multi_addr(rge_t *rgep)
1214 hashp = (uint32_t *)rgep->mcast_hash;
1219 if (rgep->chipid.mac_ver == MAC_VER_8169SC) {
1220 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1222 if (rgep->promisc) {
1223 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U);
1224 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U);
1226 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0]));
1227 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1]));
1233 if (rgep->chipid.mac_ver == MAC_VER_8169SC) {
1234 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
1238 static void rge_set_promisc(rge_t *rgep);
1242 rge_set_promisc(rge_t *rgep)
1244 if (rgep->promisc)
1245 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT);
1247 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT);
1255 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo);
1259 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo)
1263 rge_get_mac_addr(rgep);
1267 rge_set_mac_addr(rgep);
1271 rge_set_multi_addr(rgep);
1275 rge_set_multi_addr(rgep);
1276 rge_set_promisc(rgep);
1293 void rge_tx_trigger(rge_t *rgep);
1297 rge_tx_trigger(rge_t *rgep)
1299 rge_reg_put8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL);
1302 void rge_hw_stats_dump(rge_t *rgep);
1306 rge_hw_stats_dump(rge_t *rgep)
1311 if (rgep->rge_mac_state == RGE_MAC_STOPPED)
1314 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0);
1319 rgep->rge_chip_state = RGE_CHIP_ERROR;
1322 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0);
1324 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL);
1329 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START);
1339 static void rge_wake_factotum(rge_t *rgep);
1343 rge_wake_factotum(rge_t *rgep)
1345 if (rgep->factotum_flag == 0) {
1346 rgep->factotum_flag = 1;
1347 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL);
1360 rge_t *rgep = (rge_t *)arg1;
1373 mutex_enter(rgep->genlock);
1375 if (rgep->suspended) {
1376 mutex_exit(rgep->genlock);
1383 int_status = rge_reg_get16(rgep, INT_STATUS_REG);
1384 if (!(int_status & rgep->int_mask)) {
1385 mutex_exit(rgep->genlock);
1389 rgep->stats.intr++;
1395 if (rgep->chipid.is_pcie) {
1396 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE);
1399 rge_reg_put16(rgep, INT_STATUS_REG, int_status);
1405 if (now - rgep->curr_tick >= rgep->tick_delta &&
1406 (rgep->param_link_speed == RGE_SPEED_1000M ||
1407 rgep->param_link_speed == RGE_SPEED_100M)) {
1409 tx_pkts = rgep->stats.opackets - rgep->last_opackets;
1410 rx_pkts = rgep->stats.rpackets - rgep->last_rpackets;
1412 rgep->last_opackets = rgep->stats.opackets;
1413 rgep->last_rpackets = rgep->stats.rpackets;
1416 rgep->int_mask |= TX_OK_INT | RX_OK_INT;
1417 if (rgep->chipid.is_pcie) {
1418 rgep->int_mask |= NO_TXDESC_INT;
1422 if (rgep->param_link_speed == RGE_SPEED_1000M) {
1433 if (now - rgep->curr_tick < 2*rgep->tick_delta) {
1437 rgep->int_mask &= ~(TX_OK_INT | NO_TXDESC_INT);
1444 rgep->int_mask &= ~RX_OK_INT;
1452 if (rgep->chipid.is_pcie) {
1462 __func__, itimer, rgep->int_mask));
1463 rge_reg_put32(rgep, TIMER_INT_REG, itimer);
1466 rgep->curr_tick = now;
1475 rge_reg_put32(rgep, TIMER_COUNT_REG, 0);
1479 (void) rge_reg_get16(rgep, INT_STATUS_REG);
1485 rge_chip_cyclic(rgep);
1490 rgep->rx_fifo_ovf = 1;
1491 if (rgep->int_mask & RX_FIFO_OVERFLOW_INT) {
1492 rgep->int_mask &= ~RX_FIFO_OVERFLOW_INT;
1497 rgep->rx_fifo_ovf = 0;
1498 if ((rgep->int_mask & RX_FIFO_OVERFLOW_INT) == 0) {
1499 rgep->int_mask |= RX_FIFO_OVERFLOW_INT;
1504 mutex_exit(rgep->genlock);
1510 rge_receive(rgep);
1516 RGE_REPORT((rgep, "tx error happened, resetting the chip "));
1517 mutex_enter(rgep->genlock);
1518 rgep->rge_chip_state = RGE_CHIP_ERROR;
1519 mutex_exit(rgep->genlock);
1520 } else if ((rgep->chipid.is_pcie && (int_status & NO_TXDESC_INT)) ||
1521 ((int_status & TX_OK_INT) && rgep->tx_free < RGE_SEND_SLOTS/8)) {
1522 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL);
1529 RGE_REPORT((rgep, "sys error happened, resetting the chip "));
1530 mutex_enter(rgep->genlock);
1531 rgep->rge_chip_state = RGE_CHIP_ERROR;
1532 mutex_exit(rgep->genlock);
1539 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask);
1551 static boolean_t rge_factotum_link_check(rge_t *rgep);
1555 rge_factotum_link_check(rge_t *rgep)
1560 media_status = rge_reg_get8(rgep, PHY_STATUS_REG);
1563 if (rgep->param_link_up != link) {
1567 rgep->param_link_up = link;
1571 rgep->param_link_speed = RGE_SPEED_1000M;
1572 rgep->param_link_duplex = LINK_DUPLEX_FULL;
1574 rgep->param_link_speed =
1577 rgep->param_link_duplex =
1590 static boolean_t rge_factotum_stall_check(rge_t *rgep);
1594 rge_factotum_stall_check(rge_t *rgep)
1598 ASSERT(mutex_owned(rgep->genlock));
1603 rgep->rx_fifo_ovf <<= 1;
1604 if (rgep->rx_fifo_ovf > rge_rx_watchdog_count) {
1605 RGE_REPORT((rgep, "rx_hang detected"));
1623 if (rgep->resched_needed)
1624 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL);
1625 dogval = rge_atomic_shl32(&rgep->watchdog, 1);
1629 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval));
1647 rge_t *rgep;
1652 rgep = (rge_t *)arg1;
1655 if (rgep->factotum_flag == 0)
1658 rgep->factotum_flag = 0;
1663 mutex_enter(rgep->genlock);
1664 switch (rgep->rge_chip_state) {
1669 linkchg = rge_factotum_link_check(rgep);
1670 error = rge_factotum_stall_check(rgep);
1682 RGE_REPORT((rgep, "automatic recovery activated"));
1683 rge_restart(rgep);
1693 rge_chip_stop(rgep, B_TRUE);
1694 mutex_exit(rgep->genlock);
1701 mac_link_update(rgep->mh, rgep->param_link_up);
1719 rge_t *rgep;
1721 rgep = arg;
1723 switch (rgep->rge_chip_state) {
1728 rge_phy_check(rgep);
1729 if (rgep->tx_free < RGE_SEND_SLOTS)
1730 rge_send_recycle(rgep);
1738 rge_wake_factotum(rgep);
1751 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
1755 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd)
1761 (void *)rgep, (void *)ppd));
1767 regval = pci_config_get8(rgep->cfg_handle, regno);
1771 regval = pci_config_get16(rgep->cfg_handle, regno);
1775 regval = pci_config_get32(rgep->cfg_handle, regno);
1779 regval = pci_config_get64(rgep->cfg_handle, regno);
1786 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
1790 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd)
1796 (void *)rgep, (void *)ppd));
1803 pci_config_put8(rgep->cfg_handle, regno, regval);
1807 pci_config_put16(rgep->cfg_handle, regno, regval);
1811 pci_config_put32(rgep->cfg_handle, regno, regval);
1815 pci_config_put64(rgep->cfg_handle, regno, regval);
1820 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd);
1824 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd)
1830 (void *)rgep, (void *)ppd));
1832 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset);
1836 regval = ddi_get8(rgep->io_handle, regaddr);
1840 regval = ddi_get16(rgep->io_handle, regaddr);
1844 regval = ddi_get32(rgep->io_handle, regaddr);
1848 regval = ddi_get64(rgep->io_handle, regaddr);
1855 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd);
1859 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd)
1865 (void *)rgep, (void *)ppd));
1867 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset);
1872 ddi_put8(rgep->io_handle, regaddr, regval);
1876 ddi_put16(rgep->io_handle, regaddr, regval);
1880 ddi_put32(rgep->io_handle, regaddr, regval);
1884 ddi_put64(rgep->io_handle, regaddr, regval);
1889 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd);
1893 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd)
1896 (void *)rgep, (void *)ppd));
1898 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2);
1901 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd);
1905 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd)
1908 (void *)rgep, (void *)ppd));
1910 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
1913 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd);
1917 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd)
1923 (void *)rgep, (void *)ppd));
1946 (void *)rgep, (void *)ppd, regval, vaddr));
1951 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd);
1955 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd)
1961 (void *)rgep, (void *)ppd));
1967 (void *)rgep, (void *)ppd, regval, vaddr));
1988 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
1993 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
1995 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd);
2006 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd);
2074 mem_va = (uintptr_t)rgep;
2075 maxoff = sizeof (*rgep);
2089 areap = &rgep->dma_area_txdesc;
2092 areap = &rgep->dma_area_rxdesc;
2095 areap = &rgep->dma_area_stats;
2132 (*ppfn)(rgep, ppd);
2136 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2141 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
2143 ASSERT(mutex_owned(rgep->genlock));
2148 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd);
2159 return (rge_pp_ioctl(rgep, cmd, mp, iocp));
2169 rge_restart(rgep);
2178 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2183 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
2205 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd);
2209 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg);
2213 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data);
2220 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp,
2225 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
2230 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp));
2232 ASSERT(mutex_owned(rgep->genlock));
2238 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd);
2248 return (rge_diag_ioctl(rgep, cmd, mp, iocp));
2255 return (rge_mii_ioctl(rgep, cmd, mp, iocp));