Lines Matching refs:pcnp
60 #define CSR_WRITE_4(pcnp, reg, val) \
61 ddi_put32(pcnp->pcn_regshandle, (uint32_t *)(pcnp->pcn_regs + reg), val)
63 #define CSR_WRITE_2(pcnp, reg, val) \
64 ddi_put16(pcnp->pcn_regshandle, (uint16_t *)(pcnp->pcn_regs + reg), val)
66 #define CSR_READ_4(pcnp, reg) \
67 ddi_get32(pcnp->pcn_regshandle, (uint32_t *)(pcnp->pcn_regs + reg))
69 #define CSR_READ_2(pcnp, reg) \
70 ddi_get16(pcnp->pcn_regshandle, (uint16_t *)(pcnp->pcn_regs + reg))
72 #define PCN_CSR_SETBIT(pcnp, reg, x) \
73 pcn_csr_write(pcnp, reg, pcn_csr_read(pcnp, reg) | (x))
75 #define PCN_CSR_CLRBIT(pcnp, reg, x) \
76 pcn_csr_write(pcnp, reg, pcn_csr_read(pcnp, reg) & ~(x))
79 pcn_bcr_write(pcnp, reg, pcn_bcr_read(pcnp, reg) | (x))
81 #define PCN_BCR_CLRBIT(pcnp, reg, x) \
82 pcn_bcr_write(pcnp, reg, pcn_bcr_read(pcnp, reg) & ~(x))
279 pcn_t *pcnp;
340 pcnp = ddi_get_soft_state(pcn_ssp, instance);
341 pcnp->pcn_dip = dip;
342 pcnp->pcn_instance = instance;
343 pcnp->pcn_extphyaddr = -1;
345 if (ddi_get_iblock_cookie(dip, 0, &pcnp->pcn_icookie) != DDI_SUCCESS) {
346 pcn_error(pcnp->pcn_dip, "ddi_get_iblock_cookie failed");
353 mutex_init(&pcnp->pcn_xmtlock, NULL, MUTEX_DRIVER, pcnp->pcn_icookie);
354 mutex_init(&pcnp->pcn_intrlock, NULL, MUTEX_DRIVER, pcnp->pcn_icookie);
355 mutex_init(&pcnp->pcn_reglock, NULL, MUTEX_DRIVER, pcnp->pcn_icookie);
365 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&pcnp->pcn_regs, 0, 0,
366 &pcn_devattr, &pcnp->pcn_regshandle)) {
371 if (pcn_set_chipid(pcnp, (uint32_t)ssid << 16 | (uint32_t)svid) !=
376 if ((pcnp->pcn_mii = mii_alloc(pcnp, dip, &pcn_mii_ops)) == NULL)
380 mii_set_pauseable(pcnp->pcn_mii, B_FALSE, B_FALSE);
382 if ((pcn_allocrxring(pcnp) != DDI_SUCCESS) ||
383 (pcn_alloctxring(pcnp) != DDI_SUCCESS)) {
388 pcnp->pcn_promisc = B_FALSE;
390 mutex_enter(&pcnp->pcn_intrlock);
391 mutex_enter(&pcnp->pcn_xmtlock);
392 rc = pcn_initialize(pcnp, B_TRUE);
393 mutex_exit(&pcnp->pcn_xmtlock);
394 mutex_exit(&pcnp->pcn_intrlock);
398 if (ddi_add_intr(dip, 0, NULL, NULL, pcn_intr, (caddr_t)pcnp) !=
404 pcnp->pcn_flags |= PCN_INTR_ENABLED;
407 pcn_error(pcnp->pcn_dip, "mac_alloc failed");
412 macp->m_driver = pcnp;
414 macp->m_src_addr = pcnp->pcn_addr;
420 if (mac_register(macp, &pcnp->pcn_mh) == DDI_SUCCESS) {
430 pcn_teardown(pcnp);
437 pcn_t *pcnp;
439 pcnp = ddi_get_soft_state(pcn_ssp, ddi_get_instance(dip));
441 if (pcnp == NULL) {
448 if (mac_unregister(pcnp->pcn_mh) != 0)
451 mutex_enter(&pcnp->pcn_intrlock);
452 mutex_enter(&pcnp->pcn_xmtlock);
453 pcnp->pcn_flags &= ~PCN_RUNNING;
454 pcn_stopall(pcnp);
455 mutex_exit(&pcnp->pcn_xmtlock);
456 mutex_exit(&pcnp->pcn_intrlock);
458 pcn_teardown(pcnp);
462 mii_suspend(pcnp->pcn_mii);
464 mutex_enter(&pcnp->pcn_intrlock);
465 mutex_enter(&pcnp->pcn_xmtlock);
466 pcnp->pcn_flags |= PCN_SUSPENDED;
467 pcn_stopall(pcnp);
468 mutex_exit(&pcnp->pcn_xmtlock);
469 mutex_exit(&pcnp->pcn_intrlock);
480 pcn_t *pcnp;
482 if ((pcnp = ddi_get_soft_state(pcn_ssp, ddi_get_instance(dip))) == NULL)
485 mutex_enter(&pcnp->pcn_intrlock);
486 mutex_enter(&pcnp->pcn_xmtlock);
488 pcnp->pcn_flags &= ~PCN_SUSPENDED;
490 if (!pcn_initialize(pcnp, B_FALSE)) {
491 pcn_error(pcnp->pcn_dip, "unable to resume chip");
492 pcnp->pcn_flags |= PCN_SUSPENDED;
493 mutex_exit(&pcnp->pcn_intrlock);
494 mutex_exit(&pcnp->pcn_xmtlock);
498 if (IS_RUNNING(pcnp))
499 pcn_startall(pcnp);
501 mutex_exit(&pcnp->pcn_xmtlock);
502 mutex_exit(&pcnp->pcn_intrlock);
504 mii_resume(pcnp->pcn_mii);
512 pcn_t *pcnp;
514 if ((pcnp = ddi_get_soft_state(pcn_ssp, ddi_get_instance(dip))) == NULL)
518 CSR_WRITE_4(pcnp, PCN_IO32_RAP, PCN_CSR_EXTCTL1);
519 CSR_WRITE_4(pcnp, PCN_IO32_RDP, CSR_READ_4(pcnp, PCN_IO32_RDP) &
522 CSR_WRITE_4(pcnp, PCN_IO32_RAP, PCN_CSR_CSR);
523 CSR_WRITE_4(pcnp, PCN_IO32_RDP,
524 (CSR_READ_4(pcnp, PCN_IO32_RDP) & ~(PCN_CSR_INTEN)) |
531 pcn_teardown(pcn_t *pcnp)
533 ASSERT(!(pcnp->pcn_flags & PCN_RUNNING));
535 if (pcnp->pcn_mii != NULL) {
536 mii_free(pcnp->pcn_mii);
537 pcnp->pcn_mii = NULL;
540 if (pcnp->pcn_flags & PCN_INTR_ENABLED)
541 ddi_remove_intr(pcnp->pcn_dip, 0, pcnp->pcn_icookie);
544 pcn_freerxring(pcnp);
545 pcn_freetxring(pcnp);
547 if (pcnp->pcn_regshandle != NULL)
548 ddi_regs_map_free(&pcnp->pcn_regshandle);
551 mutex_destroy(&pcnp->pcn_xmtlock);
552 mutex_destroy(&pcnp->pcn_intrlock);
553 mutex_destroy(&pcnp->pcn_reglock);
555 ddi_soft_state_free(pcn_ssp, ddi_get_instance(pcnp->pcn_dip));
562 pcn_suspend(pcn_t *pcnp)
567 PCN_CSR_SETBIT(pcnp, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
569 if ((val = pcn_csr_read(pcnp, PCN_CSR_EXTCTL1)) &
575 pcn_error(pcnp->pcn_dip, "Unable to suspend, EXTCTL1 was 0x%b", val,
580 pcn_resume(pcn_t *pcnp)
582 PCN_CSR_CLRBIT(pcnp, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
588 pcn_t *pcnp = (pcn_t *)arg;
603 mutex_enter(&pcnp->pcn_intrlock);
604 mutex_enter(&pcnp->pcn_xmtlock);
605 newval = oldval = pcnp->pcn_mctab[index];
608 pcnp->pcn_mccount[crc]++;
609 if (pcnp->pcn_mccount[crc] == 1)
612 pcnp->pcn_mccount[crc]--;
613 if (pcnp->pcn_mccount[crc] == 0)
617 pcnp->pcn_mctab[index] = newval;
618 pcn_suspend(pcnp);
619 pcn_csr_write(pcnp, PCN_CSR_MAR0 + index, newval);
620 pcn_resume(pcnp);
623 mutex_exit(&pcnp->pcn_xmtlock);
624 mutex_exit(&pcnp->pcn_intrlock);
632 pcn_t *pcnp = (pcn_t *)arg;
634 mutex_enter(&pcnp->pcn_intrlock);
635 mutex_enter(&pcnp->pcn_xmtlock);
637 pcnp->pcn_promisc = on;
639 if (IS_RUNNING(pcnp))
640 pcn_suspend(pcnp);
643 if (pcnp->pcn_promisc)
644 PCN_CSR_SETBIT(pcnp, PCN_CSR_MODE, PCN_MODE_PROMISC);
646 PCN_CSR_CLRBIT(pcnp, PCN_CSR_MODE, PCN_MODE_PROMISC);
648 if (IS_RUNNING(pcnp))
649 pcn_resume(pcnp);
651 mutex_exit(&pcnp->pcn_xmtlock);
652 mutex_exit(&pcnp->pcn_intrlock);
660 pcn_t *pcnp = (pcn_t *)arg;
666 mutex_enter(&pcnp->pcn_intrlock);
667 mutex_enter(&pcnp->pcn_xmtlock);
669 if (IS_RUNNING(pcnp))
670 pcn_suspend(pcnp);
673 pcn_csr_write(pcnp, PCN_CSR_PAR0 + i, addr[i]);
675 bcopy(macaddr, pcnp->pcn_addr, ETHERADDRL);
677 if (IS_RUNNING(pcnp))
678 pcn_resume(pcnp);
680 mutex_exit(&pcnp->pcn_xmtlock);
681 mutex_exit(&pcnp->pcn_intrlock);
689 pcn_t *pcnp = (pcn_t *)arg;
692 mutex_enter(&pcnp->pcn_xmtlock);
694 if (pcnp->pcn_flags & PCN_SUSPENDED) {
696 pcnp->pcn_carrier_errors++;
700 mutex_exit(&pcnp->pcn_xmtlock);
708 if (!pcn_send(pcnp, mp)) {
714 mutex_exit(&pcnp->pcn_xmtlock);
720 pcn_send(pcn_t *pcnp, mblk_t *mp)
727 ASSERT(mutex_owned(&pcnp->pcn_xmtlock));
732 pcnp->pcn_macxmt_errors++;
737 if (pcnp->pcn_txavail < PCN_TXRECLAIM)
738 pcn_reclaim(pcnp);
740 if (pcnp->pcn_txavail == 0) {
741 pcnp->pcn_wantw = B_TRUE;
744 PCN_CSR_SETBIT(pcnp, PCN_CSR_EXTCTL1, PCN_EXTCTL1_LTINTEN);
748 txsend = pcnp->pcn_txsend;
755 txb = pcnp->pcn_txbufs[txsend];
758 pcnp->pcn_opackets++;
759 pcnp->pcn_obytes += len;
762 pcnp->pcn_multixmt++;
764 pcnp->pcn_brdcstxmt++;
767 tmd = &pcnp->pcn_txdescp[txsend];
779 SYNCTXDESC(pcnp, txsend, DDI_DMA_SYNC_FORDEV);
781 pcnp->pcn_txavail--;
782 pcnp->pcn_txsend = (txsend + 1) % PCN_TXRING;
783 pcnp->pcn_txstall_time = gethrtime() + (5 * 1000000000ULL);
785 pcn_csr_write(pcnp, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
791 pcn_reclaim(pcn_t *pcnp)
795 while (pcnp->pcn_txavail != PCN_TXRING) {
796 int index = pcnp->pcn_txreclaim;
798 tmdp = &pcnp->pcn_txdescp[index];
801 SYNCTXDESC(pcnp, index, DDI_DMA_SYNC_FORKERNEL);
807 pcnp->pcn_txavail++;
808 pcnp->pcn_txreclaim = (index + 1) % PCN_TXRING;
811 if (pcnp->pcn_txavail >= PCN_TXRESCHED) {
812 if (pcnp->pcn_wantw) {
813 pcnp->pcn_wantw = B_FALSE;
816 PCN_CSR_CLRBIT(pcnp, PCN_CSR_EXTCTL1,
819 mac_tx_update(pcnp->pcn_mh);
827 pcn_t *pcnp = (void *)arg1;
832 mutex_enter(&pcnp->pcn_intrlock);
834 if (IS_SUSPENDED(pcnp)) {
835 mutex_exit(&pcnp->pcn_intrlock);
839 while ((status = pcn_csr_read(pcnp, PCN_CSR_CSR)) & PCN_CSR_INTR) {
840 pcn_csr_write(pcnp, PCN_CSR_CSR, status);
842 status2 = pcn_csr_read(pcnp, PCN_CSR_EXTCTL2);
845 mutex_enter(&pcnp->pcn_xmtlock);
846 pcn_reclaim(pcnp);
847 mutex_exit(&pcnp->pcn_xmtlock);
851 mp = pcn_receive(pcnp);
861 PCN_CSR_SETBIT(pcnp, PCN_CSR_EXTCTL2,
864 if (pcn_watchdog(pcnp) != DDI_SUCCESS) {
872 mutex_enter(&pcnp->pcn_xmtlock);
873 pcn_resetall(pcnp);
874 mutex_exit(&pcnp->pcn_xmtlock);
875 mutex_exit(&pcnp->pcn_intrlock);
877 mii_reset(pcnp->pcn_mii);
879 mutex_exit(&pcnp->pcn_intrlock);
883 mac_rx(pcnp->pcn_mh, NULL, mp);
889 pcn_receive(pcn_t *pcnp)
899 head = pcnp->pcn_rxhead;
902 rmd = &pcnp->pcn_rxdescp[head];
903 rxb = pcnp->pcn_rxbufs[head];
905 SYNCRXDESC(pcnp, head, DDI_DMA_SYNC_FORKERNEL);
912 pcnp->pcn_errrcv++;
915 pcnp->pcn_align_errors++;
917 pcnp->pcn_overflow++;
919 pcnp->pcn_fcs_errors++;
921 pcnp->pcn_errrcv++;
922 pcnp->pcn_toolong_errors++;
926 pcnp->pcn_errrcv++;
927 pcnp->pcn_norcvbuf++;
936 pcnp->pcn_ipackets++;
937 pcnp->pcn_rbytes++;
941 pcnp->pcn_brdcstrcv++;
943 pcnp->pcn_multircv++;
951 SYNCRXDESC(pcnp, head, DDI_DMA_SYNC_FORDEV);
956 pcnp->pcn_rxhead = head;
963 pcn_t *pcnp = (pcn_t *)arg;
965 if (mii_m_loop_ioctl(pcnp->pcn_mii, wq, mp))
974 pcn_t *pcnp = (pcn_t *)arg;
976 mutex_enter(&pcnp->pcn_intrlock);
977 mutex_enter(&pcnp->pcn_xmtlock);
979 pcn_startall(pcnp);
980 pcnp->pcn_flags |= PCN_RUNNING;
982 mutex_exit(&pcnp->pcn_xmtlock);
983 mutex_exit(&pcnp->pcn_intrlock);
985 mii_start(pcnp->pcn_mii);
993 pcn_t *pcnp = (pcn_t *)arg;
995 mii_stop(pcnp->pcn_mii);
997 mutex_enter(&pcnp->pcn_intrlock);
998 mutex_enter(&pcnp->pcn_xmtlock);
1000 pcn_stopall(pcnp);
1001 pcnp->pcn_flags &= ~PCN_RUNNING;
1003 mutex_exit(&pcnp->pcn_xmtlock);
1004 mutex_exit(&pcnp->pcn_intrlock);
1008 pcn_initialize(pcn_t *pcnp, boolean_t getfact)
1013 bcopy(pcnp->pcn_addr, addr, sizeof (addr));
1022 (void) CSR_READ_2(pcnp, PCN_IO16_RESET);
1023 (void) CSR_READ_4(pcnp, PCN_IO32_RESET);
1028 CSR_WRITE_4(pcnp, PCN_IO32_RDP, 0);
1031 pcn_stop_timer(pcnp);
1034 pcn_csr_write(pcnp, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1037 pcn_bcr_write(pcnp, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI);
1041 pcn_getfactaddr(pcnp);
1043 pcn_csr_write(pcnp, PCN_CSR_PAR0, addr[0]);
1044 pcn_csr_write(pcnp, PCN_CSR_PAR1, addr[1]);
1045 pcn_csr_write(pcnp, PCN_CSR_PAR2, addr[2]);
1048 PCN_BCR_CLRBIT(pcnp, PCN_BCR_MISCCFG, PCN_MISC_ASEL);
1055 pcn_csr_write(pcnp, PCN_CSR_MODE, PCN_PORT_MII);
1058 PCN_BCR_SETBIT(pcnp, PCN_BCR_MIICTL, PCN_MIICTL_XPHYANE);
1060 if (pcnp->pcn_promisc)
1061 PCN_CSR_SETBIT(pcnp, PCN_CSR_MODE, PCN_MODE_PROMISC);
1065 pcn_csr_write(pcnp, PCN_CSR_MAR0 + i, pcnp->pcn_mctab[i]);
1067 pcn_resetrings(pcnp);
1070 pcn_csr_write(pcnp, PCN_CSR_IAB1, 0);
1077 PCN_BCR_SETBIT(pcnp, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW |
1081 PCN_CSR_SETBIT(pcnp, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1084 PCN_CSR_SETBIT(pcnp, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1086 if (pcnp->pcn_type == Am79C978)
1087 pcn_bcr_write(pcnp, PCN_BCR_PHYSEL,
1094 pcn_resetall(pcn_t *pcnp)
1096 pcn_stopall(pcnp);
1097 pcn_startall(pcnp);
1101 pcn_startall(pcn_t *pcnp)
1103 ASSERT(mutex_owned(&pcnp->pcn_intrlock));
1104 ASSERT(mutex_owned(&pcnp->pcn_xmtlock));
1106 (void) pcn_initialize(pcnp, B_FALSE);
1109 PCN_CSR_SETBIT(pcnp, PCN_CSR_CSR, PCN_CSR_START|PCN_CSR_INTEN);
1111 pcn_start_timer(pcnp);
1113 if (IS_RUNNING(pcnp))
1114 mac_tx_update(pcnp->pcn_mh);
1118 pcn_stopall(pcn_t *pcnp)
1120 ASSERT(mutex_owned(&pcnp->pcn_intrlock));
1121 ASSERT(mutex_owned(&pcnp->pcn_xmtlock));
1123 pcn_stop_timer(pcnp);
1124 PCN_CSR_SETBIT(pcnp, PCN_CSR_CSR, PCN_CSR_STOP);
1132 pcn_start_timer(pcn_t *pcnp)
1134 PCN_CSR_SETBIT(pcnp, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SINTEN);
1141 pcn_bcr_write(pcnp, PCN_BCR_TIMER, 0xa000);
1146 pcn_stop_timer(pcn_t *pcnp)
1148 PCN_CSR_CLRBIT(pcnp, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SINTEN);
1154 pcn_t *pcnp = (pcn_t *)arg;
1156 if (mii_m_getstat(pcnp->pcn_mii, stat, val) == 0)
1161 *val = pcnp->pcn_multircv;
1165 *val = pcnp->pcn_brdcstrcv;
1169 *val = pcnp->pcn_multixmt;
1173 *val = pcnp->pcn_brdcstxmt;
1177 *val = pcnp->pcn_ipackets;
1181 *val = pcnp->pcn_rbytes;
1185 *val = pcnp->pcn_opackets;
1189 *val = pcnp->pcn_obytes;
1193 *val = pcnp->pcn_norcvbuf;
1201 *val = pcnp->pcn_collisions;
1205 *val = pcnp->pcn_errrcv;
1209 *val = pcnp->pcn_errxmt;
1213 *val = pcnp->pcn_align_errors;
1217 *val = pcnp->pcn_fcs_errors;
1221 *val = pcnp->pcn_sqe_errors;
1225 *val = pcnp->pcn_defer_xmts;
1229 *val = pcnp->pcn_first_collisions;
1233 *val = pcnp->pcn_multi_collisions;
1237 *val = pcnp->pcn_tx_late_collisions;
1241 *val = pcnp->pcn_ex_collisions;
1245 *val = pcnp->pcn_macxmt_errors;
1249 *val = pcnp->pcn_carrier_errors;
1253 *val = pcnp->pcn_toolong_errors;
1257 *val = pcnp->pcn_macrcv_errors;
1261 *val = pcnp->pcn_overflow;
1265 *val = pcnp->pcn_underflow;
1269 *val = pcnp->pcn_runt;
1273 *val = pcnp->pcn_jabber;
1286 pcn_t *pcnp = (pcn_t *)arg;
1288 return (mii_m_getprop(pcnp->pcn_mii, name, num, sz, val));
1295 pcn_t *pcnp = (pcn_t *)arg;
1297 return (mii_m_setprop(pcnp->pcn_mii, name, num, sz, val));
1304 pcn_t *pcnp = arg;
1306 mii_m_propinfo(pcnp->pcn_mii, name, num, prh);
1310 pcn_watchdog(pcn_t *pcnp)
1312 if ((pcnp->pcn_txstall_time != 0) &&
1313 (gethrtime() > pcnp->pcn_txstall_time) &&
1314 (pcnp->pcn_txavail != PCN_TXRING)) {
1315 pcnp->pcn_txstall_time = 0;
1316 pcn_error(pcnp->pcn_dip, "TX stall detected!");
1326 pcn_t *pcnp = (pcn_t *)arg;
1346 if (((pcnp->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
1347 pcnp->pcn_type == Am79C973 || pcnp->pcn_type == Am79C975 ||
1348 pcnp->pcn_type == Am79C978) && pcnp->pcn_extphyaddr != -1 &&
1349 phy != pcnp->pcn_extphyaddr) {
1354 pcn_bcr_write(pcnp, PCN_BCR_MIIADDR, phy << 5 | reg);
1355 val = pcn_bcr_read(pcnp, PCN_BCR_MIIDATA) & 0xFFFF;
1360 if (((pcnp->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
1361 pcnp->pcn_type == Am79C973 || pcnp->pcn_type == Am79C975 ||
1362 pcnp->pcn_type == Am79C978) && pcnp->pcn_extphyaddr == -1)
1363 pcnp->pcn_extphyaddr = phy;
1371 pcn_t *pcnp = (pcn_t *)arg;
1373 pcn_bcr_write(pcnp, PCN_BCR_MIIADDR, reg | (phy << 5));
1374 pcn_bcr_write(pcnp, PCN_BCR_MIIDATA, val);
1380 pcn_t *pcnp = (pcn_t *)arg;
1382 mac_link_update(pcnp->pcn_mh, link);
1400 pcn_getfactaddr(pcn_t *pcnp)
1404 addr[0] = CSR_READ_4(pcnp, PCN_IO32_APROM00);
1405 addr[1] = CSR_READ_4(pcnp, PCN_IO32_APROM01);
1407 bcopy(&addr[0], &pcnp->pcn_addr[0], sizeof (pcnp->pcn_addr));
1411 pcn_csr_read(pcn_t *pcnp, uint32_t reg)
1415 mutex_enter(&pcnp->pcn_reglock);
1416 CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
1417 val = CSR_READ_4(pcnp, PCN_IO32_RDP);
1418 mutex_exit(&pcnp->pcn_reglock);
1423 pcn_csr_read16(pcn_t *pcnp, uint32_t reg)
1427 mutex_enter(&pcnp->pcn_reglock);
1428 CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg);
1429 val = CSR_READ_2(pcnp, PCN_IO16_RDP);
1430 mutex_exit(&pcnp->pcn_reglock);
1435 pcn_csr_write(pcn_t *pcnp, uint32_t reg, uint32_t val)
1437 mutex_enter(&pcnp->pcn_reglock);
1438 CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
1439 CSR_WRITE_4(pcnp, PCN_IO32_RDP, val);
1440 mutex_exit(&pcnp->pcn_reglock);
1444 pcn_bcr_read(pcn_t *pcnp, uint32_t reg)
1448 mutex_enter(&pcnp->pcn_reglock);
1449 CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
1450 val = CSR_READ_4(pcnp, PCN_IO32_BDP);
1451 mutex_exit(&pcnp->pcn_reglock);
1456 pcn_bcr_read16(pcn_t *pcnp, uint32_t reg)
1460 mutex_enter(&pcnp->pcn_reglock);
1461 CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg);
1462 val = CSR_READ_2(pcnp, PCN_IO16_BDP);
1463 mutex_exit(&pcnp->pcn_reglock);
1468 pcn_bcr_write(pcn_t *pcnp, uint32_t reg, uint32_t val)
1470 mutex_enter(&pcnp->pcn_reglock);
1471 CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
1472 CSR_WRITE_4(pcnp, PCN_IO32_BDP, val);
1473 mutex_exit(&pcnp->pcn_reglock);
1477 pcn_resetrings(pcn_t *pcnp)
1482 pcnp->pcn_rxhead = 0;
1483 pcnp->pcn_txreclaim = 0;
1484 pcnp->pcn_txsend = 0;
1485 pcnp->pcn_txavail = PCN_TXRING;
1489 pcn_rx_desc_t *rmd = &pcnp->pcn_rxdescp[i];
1490 pcn_buf_t *rxb = pcnp->pcn_rxbufs[i];
1497 (void) ddi_dma_sync(pcnp->pcn_rxdesc_dmah, 0,
1502 pcn_tx_desc_t *txd = &pcnp->pcn_txdescp[i];
1503 pcn_buf_t *txb = pcnp->pcn_txbufs[i];
1508 (void) ddi_dma_sync(pcnp->pcn_txdesc_dmah, 0,
1512 pcn_csr_write(pcnp, PCN_CSR_RXADDR0, pcnp->pcn_rxdesc_paddr & 0xFFFF);
1513 pcn_csr_write(pcnp, PCN_CSR_RXADDR1,
1514 (pcnp->pcn_rxdesc_paddr >> 16) & 0xFFFF);
1516 pcn_csr_write(pcnp, PCN_CSR_TXADDR0, pcnp->pcn_txdesc_paddr & 0xFFFF);
1517 pcn_csr_write(pcnp, PCN_CSR_TXADDR1,
1518 (pcnp->pcn_txdesc_paddr >> 16) & 0xFFFF);
1521 pcn_csr_write(pcnp, PCN_CSR_RXRINGLEN, (~PCN_RXRING) + 1);
1522 pcn_csr_write(pcnp, PCN_CSR_TXRINGLEN, (~PCN_TXRING) + 1);
1541 pcn_allocbuf(pcn_t *pcnp)
1550 if (ddi_dma_alloc_handle(pcnp->pcn_dip, &pcn_dma_attr, DDI_DMA_SLEEP,
1575 pcn_alloctxring(pcn_t *pcnp)
1587 rval = ddi_dma_alloc_handle(pcnp->pcn_dip, &pcn_dma_attr, DDI_DMA_SLEEP,
1588 NULL, &pcnp->pcn_txdesc_dmah);
1590 pcn_error(pcnp->pcn_dip, "unable to allocate DMA handle for tx "
1595 rval = ddi_dma_mem_alloc(pcnp->pcn_txdesc_dmah, size, &pcn_devattr,
1597 &pcnp->pcn_txdesc_acch);
1599 pcn_error(pcnp->pcn_dip, "unable to allocate DMA memory for tx "
1604 rval = ddi_dma_addr_bind_handle(pcnp->pcn_txdesc_dmah, NULL, kaddr,
1608 pcn_error(pcnp->pcn_dip, "unable to bind DMA for tx "
1615 pcnp->pcn_txdesc_paddr = dmac.dmac_address;
1616 pcnp->pcn_txdescp = (void *)kaddr;
1618 pcnp->pcn_txbufs = kmem_zalloc(PCN_TXRING * sizeof (pcn_buf_t *),
1622 pcn_buf_t *txb = pcn_allocbuf(pcnp);
1625 pcnp->pcn_txbufs[i] = txb;
1632 pcn_allocrxring(pcn_t *pcnp)
1644 rval = ddi_dma_alloc_handle(pcnp->pcn_dip, &pcn_dmadesc_attr,
1645 DDI_DMA_SLEEP, NULL, &pcnp->pcn_rxdesc_dmah);
1647 pcn_error(pcnp->pcn_dip, "unable to allocate DMA handle for rx "
1652 rval = ddi_dma_mem_alloc(pcnp->pcn_rxdesc_dmah, size, &pcn_devattr,
1654 &pcnp->pcn_rxdesc_acch);
1656 pcn_error(pcnp->pcn_dip, "unable to allocate DMA memory for rx "
1661 rval = ddi_dma_addr_bind_handle(pcnp->pcn_rxdesc_dmah, NULL, kaddr,
1665 pcn_error(pcnp->pcn_dip, "unable to bind DMA for rx "
1672 pcnp->pcn_rxdesc_paddr = dmac.dmac_address;
1673 pcnp->pcn_rxdescp = (void *)kaddr;
1675 pcnp->pcn_rxbufs = kmem_zalloc(PCN_RXRING * sizeof (pcn_buf_t *),
1679 pcn_buf_t *rxb = pcn_allocbuf(pcnp);
1682 pcnp->pcn_rxbufs[i] = rxb;
1689 pcn_freetxring(pcn_t *pcnp)
1693 if (pcnp->pcn_txbufs) {
1695 pcn_destroybuf(pcnp->pcn_txbufs[i]);
1697 kmem_free(pcnp->pcn_txbufs, PCN_TXRING * sizeof (pcn_buf_t *));
1700 if (pcnp->pcn_txdesc_paddr)
1701 (void) ddi_dma_unbind_handle(pcnp->pcn_txdesc_dmah);
1702 if (pcnp->pcn_txdesc_acch)
1703 ddi_dma_mem_free(&pcnp->pcn_txdesc_acch);
1704 if (pcnp->pcn_txdesc_dmah)
1705 ddi_dma_free_handle(&pcnp->pcn_txdesc_dmah);
1709 pcn_freerxring(pcn_t *pcnp)
1713 if (pcnp->pcn_rxbufs) {
1715 pcn_destroybuf(pcnp->pcn_rxbufs[i]);
1717 kmem_free(pcnp->pcn_rxbufs, PCN_RXRING * sizeof (pcn_buf_t *));
1720 if (pcnp->pcn_rxdesc_paddr)
1721 (void) ddi_dma_unbind_handle(pcnp->pcn_rxdesc_dmah);
1722 if (pcnp->pcn_rxdesc_acch)
1723 ddi_dma_mem_free(&pcnp->pcn_rxdesc_acch);
1724 if (pcnp->pcn_rxdesc_dmah)
1725 ddi_dma_free_handle(&pcnp->pcn_rxdesc_dmah);
1729 pcn_set_chipid(pcn_t *pcnp, uint32_t conf_id)
1747 chipid = pcn_bcr_read16(pcnp, PCN_BCR_PCISUBSYSID);
1749 chipid |= pcn_bcr_read16(pcnp, PCN_BCR_PCISUBVENID);
1759 chipid = pcn_csr_read16(pcnp, PCN_CSR_CHIPID1);
1761 chipid |= pcn_csr_read16(pcnp, PCN_CSR_CHIPID0);
1763 chipid = pcn_csr_read(pcnp, PCN_CSR_CHIPID1);
1765 chipid |= pcn_csr_read(pcnp, PCN_CSR_CHIPID0);
1774 pcn_error(pcnp->pcn_dip, "Unsupported chip: %s", name);
1778 pcn_error(pcnp->pcn_dip, "Unsupported chip: %s", name);
1800 pcn_error(pcnp->pcn_dip, "Unknown chip id 0x%x", chipid);
1803 if (ddi_prop_update_string(DDI_DEV_T_NONE, pcnp->pcn_dip, "chipid",
1805 pcn_error(pcnp->pcn_dip, "Unable to set chipid property");