Lines Matching refs:pwr_p
136 static int pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p);
1542 pcie_pwr_t *pwr_p;
1551 pwr_p = PCIE_NEXUS_PMINFO(dip);
1552 ASSERT(pwr_p);
1555 if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) {
1560 conf_hdl = pwr_p->pwr_conf_hdl;
1575 pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR;
1579 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1;
1583 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2;
1589 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2)
1591 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D1)
1605 return (pcieb_pwr_init_and_raise(dip, pwr_p));
1614 pcie_pwr_t *pwr_p;
1616 if (!PCIE_PMINFO(dip) || !(pwr_p = PCIE_NEXUS_PMINFO(dip)))
1620 if (pwr_p->pwr_conf_hdl)
1621 pci_config_teardown(&pwr_p->pwr_conf_hdl);
1629 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p)
1639 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, pwr_p->pwr_pmcsr_offset);
1643 pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1647 pwr_p->pwr_func_lvl = PM_LEVEL_D1;
1651 pwr_p->pwr_func_lvl = PM_LEVEL_D2;
1655 pwr_p->pwr_func_lvl = PM_LEVEL_D3;
1663 if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 &&
1669 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl,
1670 pwr_p->pwr_pmcsr_offset);
1679 pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1692 pcie_pwr_t *pwr_p;
1695 pwr_p = PCIE_NEXUS_PMINFO(dip);
1696 ASSERT(pwr_p);
1698 pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1699 pwr_p->pwr_flags = PCIE_NO_CHILD_PM;