Lines Matching defs:pfd_p
68 #define HAS_AER_LOGS(pfd_p, bit) \
69 (PCIE_HAS_AER(pfd_p->pe_bus_p) && \
70 PF_FIRST_AER_ERR(bit, PCIE_ADV_REG(pfd_p)))
75 #define HAS_SAER_LOGS(pfd_p, bit) \
76 (PCIE_HAS_AER(pfd_p->pe_bus_p) && \
77 PF_FIRST_SAER_ERR(bit, PCIE_ADV_BDG_REG(pfd_p)))
79 #define GET_SAER_CMD(pfd_p) \
80 ((PCIE_ADV_BDG_HDR(pfd_p, 1) >> \
83 #define CE_ADVISORY(pfd_p) \
84 (PCIE_ADV_REG(pfd_p)->pcie_ce_status & PCIE_AER_CE_AD_NFE)
108 static void pf_pcix_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p);
109 static void pf_pcie_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p);
110 static void pf_pci_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p);
112 static void pf_en_dq(pf_data_t *pfd_p, pf_impl_t *impl_p);
176 pf_data_t *pfd_p;
182 for (pfd_p = root_pfd_p; pfd_p; pfd_p = pfd_p->pe_next) {
183 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = 0;
184 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = PCIE_INVALID_BDF;
185 if (PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p))) {
186 PCIE_ROOT_EH_SRC(pfd_p)->intr_type = PF_INTR_TYPE_NONE;
187 PCIE_ROOT_EH_SRC(pfd_p)->intr_data = NULL;
214 pf_data_t *pfd_p, *pfd_head_p, *pfd_tail_p;
255 for (pfd_p = impl.pf_dq_head_p; pfd_p && PFD_IS_ROOT(pfd_p);
256 pfd_p = pfd_p->pe_next) {
257 impl.pf_fault = PCIE_ROOT_FAULT(pfd_p);
259 if (PFD_IS_RC(pfd_p))
369 pf_data_t *pfd_p = PCIE_BUS2PFD(bus_p);
370 pf_pci_err_regs_t *err_p = PCI_ERR_REG(pfd_p);
371 pf_pci_bdg_err_regs_t *serr_p = PCI_BDG_ERR_REG(pfd_p);
518 pf_pcix_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p)
528 pcix_bdg_regs = PCIX_BDG_ERR_REG(pfd_p);
545 PCIX_BDG_ECC_REG(pfd_p, 0), bus_p, B_TRUE);
549 pf_pcix_ecc_regs_gather(PCIX_BDG_ECC_REG(pfd_p, 0),
553 pf_pcix_err_regs_t *pcix_regs = PCIX_ERR_REG(pfd_p);
560 pf_pcix_ecc_regs_gather(PCIX_ECC_REG(pfd_p), bus_p,
566 pf_pcie_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p)
568 pf_pcie_err_regs_t *pcie_regs = PCIE_ERR_REG(pfd_p);
569 pf_pcie_adv_err_regs_t *pcie_adv_regs = PCIE_ADV_REG(pfd_p);
576 pf_pcix_regs_gather(pfd_p, bus_p);
579 pf_pcie_rp_err_regs_t *pcie_rp_regs = PCIE_RP_REG(pfd_p);
599 PCIE_ADV_HDR(pfd_p, 0) = PCIE_AER_GET(32, bus_p,
601 PCIE_ADV_HDR(pfd_p, 1) = PCIE_AER_GET(32, bus_p,
603 PCIE_ADV_HDR(pfd_p, 2) = PCIE_AER_GET(32, bus_p,
605 PCIE_ADV_HDR(pfd_p, 3) = PCIE_AER_GET(32, bus_p,
620 PCIE_ADV_BDG_REG(pfd_p);
630 PCIE_ADV_BDG_HDR(pfd_p, 0) = PCIE_AER_GET(32, bus_p,
632 PCIE_ADV_BDG_HDR(pfd_p, 1) = PCIE_AER_GET(32, bus_p,
634 PCIE_ADV_BDG_HDR(pfd_p, 2) = PCIE_AER_GET(32, bus_p,
636 PCIE_ADV_BDG_HDR(pfd_p, 3) = PCIE_AER_GET(32, bus_p,
646 PCIE_ADV_RP_REG(pfd_p);
660 pf_pci_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p)
662 pf_pci_err_regs_t *pci_regs = PCI_ERR_REG(pfd_p);
675 pf_pci_bdg_err_regs_t *pci_bdg_regs = PCI_BDG_ERR_REG(pfd_p);
688 pf_pcie_regs_gather(pfd_p, bus_p);
690 pf_pcix_regs_gather(pfd_p, bus_p);
695 pf_pcix_regs_clear(pf_data_t *pfd_p, pcie_bus_t *bus_p)
700 pcix_bdg_regs = PCIX_BDG_ERR_REG(pfd_p);
717 pcix_bdg_ecc_regs = PCIX_BDG_ECC_REG(pfd_p, 0);
722 pcix_bdg_ecc_regs = PCIX_BDG_ECC_REG(pfd_p, 1);
727 pf_pcix_err_regs_t *pcix_regs = PCIX_ERR_REG(pfd_p);
733 pf_pcix_ecc_regs_t *pcix_ecc_regs = PCIX_ECC_REG(pfd_p);
742 pf_pcie_regs_clear(pf_data_t *pfd_p, pcie_bus_t *bus_p)
744 pf_pcie_err_regs_t *pcie_regs = PCIE_ERR_REG(pfd_p);
745 pf_pcie_adv_err_regs_t *pcie_adv_regs = PCIE_ADV_REG(pfd_p);
750 pf_pcix_regs_clear(pfd_p, bus_p);
763 PCIE_ADV_BDG_REG(pfd_p);
776 pcie_rp_regs = PCIE_ADV_RP_REG(pfd_p);
784 pf_pci_regs_clear(pf_data_t *pfd_p, pcie_bus_t *bus_p)
787 pf_pcie_regs_clear(pfd_p, bus_p);
789 pf_pcix_regs_clear(pfd_p, bus_p);
791 PCIE_PUT(16, bus_p, PCI_CONF_STAT, pfd_p->pe_pci_regs->pci_err_status);
794 pf_pci_bdg_err_regs_t *pci_bdg_regs = PCI_BDG_ERR_REG(pfd_p);
805 pf_data_t *pfd_p = PCIE_DIP2PFD(dip);
809 pf_pci_regs_gather(pfd_p, bus_p);
810 pf_pci_regs_clear(pfd_p, bus_p);
815 pf_pci_find_rp_fault(pf_data_t *pfd_p, pcie_bus_t *bus_p)
817 pf_root_fault_t *root_fault = PCIE_ROOT_FAULT(pfd_p);
818 pf_pcie_adv_rp_err_regs_t *rp_regs = PCIE_ADV_RP_REG(pfd_p);
820 uint32_t ue_err = PCIE_ADV_REG(pfd_p)->pcie_ue_status;
829 (PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat & PF_PCI_BDG_ERR)) {
830 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_TRUE;
842 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_TRUE;
864 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_TRUE;
870 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = rp_regs->pcie_rp_ce_src_id;
873 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = rp_regs->pcie_rp_ue_src_id;
875 } else if ((HAS_AER_LOGS(pfd_p, PCIE_AER_UCE_CA) ||
876 HAS_AER_LOGS(pfd_p, PCIE_AER_UCE_UR)) &&
877 (pf_tlp_decode(PCIE_PFD2BUS(pfd_p), PCIE_ADV_REG(pfd_p)) ==
879 PCIE_ROOT_FAULT(pfd_p)->scan_addr =
880 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr;
888 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_TRUE;
910 pf_data_t *pfd_p = PCIE_DIP2PFD(dip);
914 if (pfd_p->pe_valid == B_TRUE) {
938 pf_reset_pfd(pfd_p);
939 pfd_p->pe_severity_flags = PF_ERR_PANIC_BAD_RESPONSE;
940 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = PF_AFFECTED_SELF;
943 pf_en_dq(pfd_p, impl);
944 pfd_p->pe_valid = B_TRUE;
949 pf_pci_regs_gather(pfd_p, bus_p);
950 pf_pci_regs_clear(pfd_p, bus_p);
952 pf_pci_find_rp_fault(pfd_p, bus_p);
960 pf_en_dq(pfd_p, impl);
972 !(PCIE_ERR_REG(pfd_p)->pcie_err_status & PF_PCIE_BDG_ERR) &&
973 !(PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat & PF_PCI_BDG_ERR))
977 !(PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat & PF_PCI_BDG_ERR))
980 pfd_p->pe_valid = B_TRUE;
1106 pf_en_dq(pf_data_t *pfd_p, pf_impl_t *impl)
1114 ASSERT(PFD_IS_ROOT(pfd_p));
1115 impl->pf_dq_head_p = pfd_p;
1116 impl->pf_dq_tail_p = pfd_p;
1117 pfd_p->pe_prev = NULL;
1118 pfd_p->pe_next = NULL;
1123 if (PFD_IS_ROOT(pfd_p)) {
1133 root_p->pe_next = pfd_p;
1134 pfd_p->pe_prev = root_p;
1135 pfd_p->pe_next = last_p;
1138 last_p->pe_prev = pfd_p;
1140 tail_p = pfd_p;
1142 tail_p->pe_next = pfd_p;
1143 pfd_p->pe_prev = tail_p;
1144 pfd_p->pe_next = NULL;
1145 tail_p = pfd_p;
1360 #define PF_MASKED_AER_ERR(pfd_p) \
1361 (PCIE_ADV_REG(pfd_p)->pcie_ue_status & \
1362 ((PCIE_ADV_REG(pfd_p)->pcie_ue_mask) ^ 0xFFFFFFFF))
1363 #define PF_MASKED_SAER_ERR(pfd_p) \
1364 (PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status & \
1365 ((PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_mask) ^ 0xFFFFFFFF))
1374 pf_data_t *pfd_p;
1376 for (pfd_p = impl->pf_dq_head_p; pfd_p; pfd_p = pfd_p->pe_next) {
1380 if (pfd_p->pe_severity_flags == PF_ERR_PANIC_BAD_RESPONSE)
1383 switch (PCIE_PFD2BUS(pfd_p)->bus_dev_type) {
1387 PCIE_ERR_REG(pfd_p)->pcie_err_status)
1390 pf_adjust_for_no_aer(pfd_p);
1392 pfd_p, pcie_pcie_tbl, PF_MASKED_AER_ERR(pfd_p));
1395 pf_adjust_for_no_aer(pfd_p);
1397 pfd_p, pcie_rp_tbl, PF_MASKED_AER_ERR(pfd_p));
1402 sts_flags |= pfd_p->pe_severity_flags;
1403 sts_flags |= pf_analyse_error_tbl(derr, impl, pfd_p,
1404 pcie_rp_tbl, PF_MASKED_AER_ERR(pfd_p));
1409 PCIE_ERR_REG(pfd_p)->pcie_err_status)
1412 pf_adjust_for_no_aer(pfd_p);
1414 pfd_p, pcie_sw_tbl, PF_MASKED_AER_ERR(pfd_p));
1418 PCIE_ERR_REG(pfd_p)->pcie_err_status)
1421 pf_adjust_for_no_aer(pfd_p);
1422 pf_adjust_for_no_saer(pfd_p);
1424 impl, pfd_p, pcie_pcie_tbl,
1425 PF_MASKED_AER_ERR(pfd_p));
1427 impl, pfd_p, pcie_pcie_bdg_tbl,
1428 PF_MASKED_SAER_ERR(pfd_p));
1435 & PCIE_ERR_REG(pfd_p)->pcie_err_status)
1440 pfd_p, pcie_pci_tbl,
1441 PCI_ERR_REG(pfd_p)->pci_err_status);
1443 if (!PCIE_IS_BDG(PCIE_PFD2BUS(pfd_p)))
1447 impl, pfd_p, pcie_pci_bdg_tbl,
1448 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat);
1451 pfd_p->pe_severity_flags = sts_flags;
1454 pfd_p->pe_orig_severity_flags = pfd_p->pe_severity_flags;
1456 pfd_p->pe_severity_flags = pciev_eh(pfd_p, impl);
1458 error_flags |= pfd_p->pe_severity_flags;
1466 pf_data_t *pfd_p, const pf_fab_err_tbl_t *tbl, uint32_t err_reg)
1477 err |= row->handler(derr, bit, impl->pf_dq_head_p, pfd_p);
1485 if (!HAS_AER_LOGS(pfd_p, bit)) {
1489 if (!HAS_SAER_LOGS(pfd_p, bit)) {
1494 if (PCIE_ROOT_FAULT(pfd_p)->scan_addr == 0) {
1499 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags |= flags;
1518 pf_data_t *pfd_p)
1521 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip;
1532 if (PCIE_IS_RP(PCIE_PFD2BUS(pfd_p)))
1540 if (pf_matched_in_rc(dq_head_p, pfd_p, abort_type))
1544 if (HAS_AER_LOGS(pfd_p, bit) &&
1545 pf_log_hdl_lookup(rpdip, derr, pfd_p, B_TRUE) == PF_HDL_FOUND)
1561 pf_data_t *pfd_p)
1563 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip;
1576 if (pf_matched_in_rc(dq_head_p, pfd_p, abort_type))
1579 if (!HAS_SAER_LOGS(pfd_p, bit))
1582 if (pf_log_hdl_lookup(rpdip, derr, pfd_p, B_FALSE) == PF_HDL_FOUND)
1599 pf_data_t *pfd_p)
1604 pcie_bus_t *bus_p = PCIE_PFD2BUS(pfd_p);
1607 if (PCI_ERR_REG(pfd_p)->pci_err_status & PCI_STAT_S_SYSERR)
1624 parent_pfd_p = pf_get_parent_pcie_bridge(pfd_p);
1673 pf_data_t *pfd_p)
1675 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip;
1682 if (HAS_SAER_LOGS(pfd_p, bit)) {
1683 saer_p = PCIE_ADV_BDG_REG(pfd_p);
1684 if (pf_pci_decode(pfd_p, &cmd) != DDI_SUCCESS)
1695 hdl_sts = pf_log_hdl_lookup(rpdip, derr, pfd_p,
1703 if (pf_matched_in_rc(dq_head_p, pfd_p,
1709 hdl_sts = pf_log_hdl_lookup(rpdip, derr, pfd_p,
1713 hdl_sts = pf_log_hdl_lookup(rpdip, derr, pfd_p,
1717 cmd = (PCIE_ADV_BDG_HDR(pfd_p, 1) >>
1737 if ((PCIE_ERR_REG(pfd_p)->pcie_err_status &
1739 pf_matched_in_rc(dq_head_p, pfd_p, PCI_STAT_R_MAST_AB))
1743 if (PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat &
1753 if (PCI_ERR_REG(pfd_p)->pci_err_status &
1773 pf_data_t *pfd_p)
1775 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip;
1781 if (HAS_AER_LOGS(pfd_p, bit)) {
1782 pcie_tlp_hdr_t *hdr = (pcie_tlp_hdr_t *)&PCIE_ADV_HDR(pfd_p, 0);
1789 if (pf_log_hdl_lookup(rpdip, derr, pfd_p, B_TRUE) ==
1799 if (PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr)
1816 if (!PFD_IS_ROOT(pfd_p)) {
1817 dev_info_t *pdip = ddi_get_parent(PCIE_PFD2DIP(pfd_p));
1820 if (PCIE_PFD2BUS(pfd_p)->bus_rp_dip == pdip) {
1821 if (pf_matched_in_rc(dq_head_p, pfd_p, PCI_STAT_PERROR))
1837 if (!PCIE_HAS_AER(PCIE_PFD2BUS(pfd_p)))
1840 secbus = PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf;
1845 bdg_pfd_p = pf_get_pcie_bridge(pfd_p, secbus);
1850 PCIE_AER_SUCE_PERR_ASSERT, dq_head_p, pfd_p);
1865 pf_data_t *pfd_p)
1867 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip;
1871 if (!HAS_SAER_LOGS(pfd_p, bit))
1874 if (pf_pci_decode(pfd_p, &cmd) != DDI_SUCCESS)
1878 sts = pf_log_hdl_lookup(rpdip, derr, pfd_p, B_FALSE);
1894 pf_data_t *pfd_p)
1896 if (HAS_AER_LOGS(pfd_p, bit) && CE_ADVISORY(pfd_p))
1910 pf_data_t *pfd_p)
1912 if (HAS_AER_LOGS(pfd_p, bit) &&
1913 (PCIE_PFD2BUS(pfd_p)->bus_bdf == (PCIE_ADV_HDR(pfd_p, 2) >> 16)))
1920 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = PF_AFFECTED_ROOT;
1937 pf_data_t *pfd_p)
1939 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip;
1941 if (!HAS_SAER_LOGS(pfd_p, bit))
1944 if (pf_matched_in_rc(dq_head_p, pfd_p, PCI_STAT_PERROR))
1947 if (pf_log_hdl_lookup(rpdip, derr, pfd_p, B_FALSE) == PF_HDL_FOUND)
1956 pf_data_t *pfd_p)
1964 pf_data_t *pfd_p)
1974 pf_adjust_for_no_aer(pf_data_t *pfd_p)
1979 if (PCIE_HAS_AER(PCIE_PFD2BUS(pfd_p)))
1982 if (PCIE_ERR_REG(pfd_p)->pcie_err_status & PCIE_DEVSTS_FE_DETECTED)
1985 if (PCIE_ERR_REG(pfd_p)->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED) {
1987 status = PCI_ERR_REG(pfd_p)->pci_err_status;
1998 if (!(PCIE_ERR_REG(pfd_p)->pcie_err_status &
2023 if (!PCIE_IS_BDG(PCIE_PFD2BUS(pfd_p))) {
2028 PCIE_ADV_REG(pfd_p)->pcie_ue_status = aer_ue;
2032 pf_adjust_for_no_saer(pf_data_t *pfd_p)
2037 if (PCIE_HAS_AER(PCIE_PFD2BUS(pfd_p)))
2040 if (PCIE_ERR_REG(pfd_p)->pcie_err_status & PCIE_DEVSTS_FE_DETECTED)
2043 if (PCIE_ERR_REG(pfd_p)->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED) {
2045 status = PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat;
2064 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status = s_aer_ue;
2069 pf_get_pcie_bridge(pf_data_t *pfd_p, pcie_req_id_t secbus)
2074 for (bdg_pfd_p = pfd_p->pe_next; bdg_pfd_p;
2086 pf_get_parent_pcie_bridge(pf_data_t *pfd_p)
2088 dev_info_t *dip, *rp_dip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip;
2091 if (!PCIE_IS_PCI(PCIE_PFD2BUS(pfd_p)))
2098 for (dip = PCIE_PFD2DIP(pfd_p); dip; dip = ddi_get_parent(dip)) {
2125 pf_matched_in_rc(pf_data_t *dq_head_p, pf_data_t *pfd_p,
2128 pcie_bus_t *bus_p = PCIE_PFD2BUS(pfd_p);
2167 pf_pci_find_trans_type(pf_data_t *pfd_p, uint64_t *addr, uint32_t *trans_type,
2172 switch (PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status) {
2195 for (rc_pfd_p = pfd_p->pe_prev; rc_pfd_p;
2219 pf_pci_decode(pf_data_t *pfd_p, uint16_t *cmd) {
2225 attr = (pcix_attr_t *)&PCIE_ADV_BDG_HDR(pfd_p, 0);
2226 *cmd = GET_SAER_CMD(pfd_p);
2233 addr = PCIE_ADV_BDG_HDR(pfd_p, 2);
2243 addr = ((uint64_t)PCIE_ADV_BDG_HDR(pfd_p, 3) <<
2244 PCIE_AER_SUCE_HDR_ADDR_SHIFT) | PCIE_ADV_BDG_HDR(pfd_p, 2);
2247 pf_pci_find_trans_type(pfd_p, &addr, &trans_type, &bdf);
2273 *cmd = (PCIE_ADV_BDG_HDR(pfd_p, 1) >>
2280 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_trans = 0;
2281 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf = PCIE_INVALID_BDF;
2282 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_addr = 0;
2285 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_trans = trans_type;
2286 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf = bdf;
2287 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_addr = addr;
2492 pf_log_hdl_lookup(dev_info_t *rpdip, ddi_fm_error_t *derr, pf_data_t *pfd_p,
2681 pf_data_t *pfd_p;
2689 for (pfd_p = impl->pf_dq_head_p; pfd_p; pfd_p = pfd_p->pe_next) {
2690 bus_p = PCIE_PFD2BUS(pfd_p);
2691 pfd_p->pe_valid = B_FALSE;
2694 !DDI_FM_EREPORT_CAP(ddi_fm_capable(PCIE_PFD2DIP(pfd_p))))
2701 if (PFD_IS_RC(pfd_p)) {
2704 PCIE_ROOT_FAULT(pfd_p)->scan_bdf,
2706 PCIE_ROOT_FAULT(pfd_p)->scan_addr,
2708 PCIE_ROOT_EH_SRC(pfd_p)->intr_type,
2731 PCI_ERR_REG(pfd_p)->pci_err_status,
2733 PCI_ERR_REG(pfd_p)->pci_cfg_comm,
2740 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat,
2742 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_ctrl,
2750 PCIX_ERR_REG(pfd_p)->pcix_status,
2752 PCIX_ERR_REG(pfd_p)->pcix_command,
2762 ecc_bdg_reg = PCIX_BDG_ECC_REG(pfd_p, 0);
2763 ecc_reg = PCIX_ECC_REG(pfd_p);
2792 ecc_bdg_reg = PCIX_BDG_ECC_REG(pfd_p, 1);
2811 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_stat,
2813 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_sec_stat,
2821 PCIE_ERR_REG(pfd_p)->pcie_err_status,
2823 PCIE_ERR_REG(pfd_p)->pcie_err_ctl,
2825 PCIE_ERR_REG(pfd_p)->pcie_dev_cap,
2833 PCIE_ADV_REG(pfd_p)->pcie_adv_ctl,
2835 PCIE_ADV_REG(pfd_p)->pcie_ue_status,
2837 PCIE_ADV_REG(pfd_p)->pcie_ue_mask,
2839 PCIE_ADV_REG(pfd_p)->pcie_ue_sev,
2841 PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[0],
2843 PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[1],
2845 PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[2],
2847 PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[3],
2849 PCIE_ADV_REG(pfd_p)->pcie_ce_status,
2851 PCIE_ADV_REG(pfd_p)->pcie_ce_mask,
2856 if (HAS_AER_LOGS(pfd_p, PCIE_ADV_REG(pfd_p)->pcie_ue_status)) {
2859 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_trans,
2861 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr,
2863 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf,
2866 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_trans = 0;
2867 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr = 0;
2868 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf = PCIE_INVALID_BDF;
2875 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_ctl,
2877 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status,
2879 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_mask,
2881 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_sev,
2883 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[0],
2885 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[1],
2887 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[2],
2889 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[3],
2894 if (PCIE_IS_PCIE_BDG(bus_p) && HAS_SAER_LOGS(pfd_p,
2895 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status)) {
2898 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_trans,
2900 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_addr,
2902 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf,
2905 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_trans = 0;
2906 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_addr = 0;
2907 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf =
2915 PCIE_RP_REG(pfd_p)->pcie_rp_status,
2917 PCIE_RP_REG(pfd_p)->pcie_rp_ctl,
2925 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_err_status,
2927 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_err_cmd,
2929 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ce_src_id,
2931 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ue_src_id,
2940 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags,
2942 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf,
2944 pfd_p->pe_orig_severity_flags,
2951 "severity", DATA_TYPE_UINT32, pfd_p->pe_severity_flags,
2959 for (pfd_p = impl->pf_dq_tail_p; pfd_p; pfd_p = pfd_p->pe_prev) {
2960 if (pfd_p->pe_lock) {
2961 pf_handler_exit(PCIE_PFD2DIP(pfd_p));
2983 pf_data_t *pfd_p = PCIE_DIP2PFD(dip);
2985 ASSERT(pfd_p);
2991 if (!pfd_p->pe_lock || !impl) {
2993 pfd_p->pe_lock = B_TRUE;
2998 for (pfd_p = impl->pf_dq_head_p; pfd_p; pfd_p = pfd_p->pe_next) {
2999 if (PCIE_PFD2DIP(pfd_p) == dip) {
3010 pf_data_t *pfd_p = PCIE_DIP2PFD(dip);
3012 ASSERT(pfd_p);
3014 ASSERT(pfd_p->pe_lock == B_TRUE);
3016 pfd_p->pe_lock = B_FALSE;
3048 pf_reset_pfd(pf_data_t *pfd_p)
3050 pcie_bus_t *bus_p = PCIE_PFD2BUS(pfd_p);
3052 pfd_p->pe_severity_flags = 0;
3053 pfd_p->pe_orig_severity_flags = 0;
3056 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = 0;
3057 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = PCIE_INVALID_BDF;
3060 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = PCIE_INVALID_BDF;
3061 PCIE_ROOT_FAULT(pfd_p)->scan_addr = 0;
3062 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_FALSE;
3063 PCIE_ROOT_EH_SRC(pfd_p)->intr_type = PF_INTR_TYPE_NONE;
3064 PCIE_ROOT_EH_SRC(pfd_p)->intr_data = NULL;
3068 bzero(PCI_BDG_ERR_REG(pfd_p), sizeof (pf_pci_bdg_err_regs_t));
3071 PCI_ERR_REG(pfd_p)->pci_err_status = 0;
3072 PCI_ERR_REG(pfd_p)->pci_cfg_comm = 0;
3076 bzero(PCIE_RP_REG(pfd_p),
3078 bzero(PCIE_ADV_RP_REG(pfd_p),
3080 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ce_src_id =
3082 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ue_src_id =
3085 bzero(PCIE_ADV_BDG_REG(pfd_p),
3087 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf =
3093 bzero(PCIX_BDG_ECC_REG(pfd_p, 0),
3095 bzero(PCIX_BDG_ECC_REG(pfd_p, 1),
3098 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_sec_stat = 0;
3099 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_stat = 0;
3102 PCIE_ADV_REG(pfd_p)->pcie_adv_ctl = 0;
3103 PCIE_ADV_REG(pfd_p)->pcie_ue_status = 0;
3104 PCIE_ADV_REG(pfd_p)->pcie_ue_mask = 0;
3105 PCIE_ADV_REG(pfd_p)->pcie_ue_sev = 0;
3106 PCIE_ADV_HDR(pfd_p, 0) = 0;
3107 PCIE_ADV_HDR(pfd_p, 1) = 0;
3108 PCIE_ADV_HDR(pfd_p, 2) = 0;
3109 PCIE_ADV_HDR(pfd_p, 3) = 0;
3110 PCIE_ADV_REG(pfd_p)->pcie_ce_status = 0;
3111 PCIE_ADV_REG(pfd_p)->pcie_ce_mask = 0;
3112 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_trans = 0;
3113 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr = 0;
3114 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf = PCIE_INVALID_BDF;
3116 PCIE_ERR_REG(pfd_p)->pcie_err_status = 0;
3117 PCIE_ERR_REG(pfd_p)->pcie_err_ctl = 0;
3118 PCIE_ERR_REG(pfd_p)->pcie_dev_cap = 0;
3123 bzero(PCIX_BDG_ECC_REG(pfd_p, 0),
3125 bzero(PCIX_BDG_ECC_REG(pfd_p, 1),
3128 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_sec_stat = 0;
3129 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_stat = 0;
3132 bzero(PCIX_ECC_REG(pfd_p),
3135 PCIX_ERR_REG(pfd_p)->pcix_command = 0;
3136 PCIX_ERR_REG(pfd_p)->pcix_status = 0;
3140 pfd_p->pe_prev = NULL;
3141 pfd_p->pe_next = NULL;
3142 pfd_p->pe_rber_fatal = B_FALSE;
3184 pf_find_busp_by_aer(pf_impl_t *impl, pf_data_t *pfd_p)
3186 pf_pcie_adv_err_regs_t *reg_p = PCIE_ADV_REG(pfd_p);
3213 pf_find_busp_by_saer(pf_impl_t *impl, pf_data_t *pfd_p)
3215 pf_pcie_adv_bdg_err_regs_t *reg_p = PCIE_ADV_BDG_REG(pfd_p);