Lines Matching refs:bus_p
58 static void pcie_print_bus(pcie_bus_t *bus_p);
286 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
289 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) {
291 } else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) {
306 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
309 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) {
311 } else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) {
328 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
339 if ((bus_p->bus_soft_state == PCI_SOFT_STATE_OPEN_EXCL) ||
341 (bus_p->bus_soft_state != PCI_SOFT_STATE_CLOSED))) {
346 bus_p->bus_soft_state = PCI_SOFT_STATE_OPEN_EXCL;
348 bus_p->bus_soft_state = PCI_SOFT_STATE_OPEN;
357 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
362 bus_p->bus_soft_state = PCI_SOFT_STATE_CLOSED;
443 pcie_bus_t *bus_p;
446 bus_p = PCIE_DIP2BUS(cdip);
447 if (bus_p == NULL)
453 " for BDF 0x%x\n", bus_p->bus_bdf);
457 bus_p->bus_cfg_hdl = eh;
464 pcie_bus_t *bus_p = PCIE_DIP2BUS(cdip);
466 pci_config_teardown(&bus_p->bus_cfg_hdl);
483 pcie_bus_t *bus_p;
486 bus_p = PCIE_DIP2BUS(cdip);
487 if (bus_p == NULL) {
518 bus_p->bus_dev_ven_id = (devid << 16) | (venid & 0xffff);
521 reg16 = PCIE_GET(16, bus_p, PCI_CONF_STAT);
522 PCIE_PUT(16, bus_p, PCI_CONF_STAT, reg16);
525 reg16 = PCIE_GET(16, bus_p, PCI_CONF_COMM);
535 pcie_check_io_mem_range(bus_p->bus_cfg_hdl, &empty_io_range,
541 ddi_driver_name(cdip), bus_p->bus_bdf);
547 ddi_driver_name(cdip), bus_p->bus_bdf);
551 if (pcie_serr_disable_flag && PCIE_IS_PCIE(bus_p))
554 PCIE_PUT(16, bus_p, PCI_CONF_COMM, tmp16);
555 PCIE_DBG_CFG(cdip, bus_p, "COMMAND", 16, PCI_CONF_COMM, reg16);
561 if (PCIE_IS_BDG(bus_p)) {
563 reg16 = PCIE_GET(16, bus_p, PCI_BCNF_SEC_STATUS);
564 PCIE_PUT(16, bus_p, PCI_BCNF_SEC_STATUS, reg16);
567 reg16 = PCIE_GET(16, bus_p, PCI_BCNF_BCNTRL);
576 if (bus_p->bus_dev_ven_id == 0x037010DE)
593 PCIE_PUT(16, bus_p, PCI_BCNF_BCNTRL, tmp16);
594 PCIE_DBG_CFG(cdip, bus_p, "SEC CMD", 16, PCI_BCNF_BCNTRL,
598 if (PCIE_IS_PCIE(bus_p)) {
600 reg16 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL);
606 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, tmp16);
607 PCIE_DBG_CAP(cdip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, reg16);
613 bus_p->bus_ari = B_FALSE;
617 bus_p->bus_ari = B_TRUE;
632 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
636 pfd_p->pe_bus_p = bus_p;
643 if (PCIE_IS_ROOT(bus_p)) {
653 if (PCIE_IS_BDG(bus_p))
656 if (PCIE_IS_PCIE(bus_p)) {
659 if (PCIE_IS_RP(bus_p))
666 if (PCIE_IS_RP(bus_p)) {
673 } else if (PCIE_IS_PCIE_BDG(bus_p)) {
680 if (PCIE_IS_PCIE_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) {
684 if (PCIX_ECC_VERSION_CHECK(bus_p)) {
691 } else if (PCIE_IS_PCIX(bus_p)) {
692 if (PCIE_IS_BDG(bus_p)) {
696 if (PCIX_ECC_VERSION_CHECK(bus_p)) {
705 if (PCIX_ECC_VERSION_CHECK(bus_p))
716 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
718 if (PCIE_IS_PCIE(bus_p)) {
719 if (PCIE_IS_PCIE_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) {
720 if (PCIX_ECC_VERSION_CHECK(bus_p)) {
731 if (PCIE_IS_RP(bus_p))
734 else if (PCIE_IS_PCIE_BDG(bus_p))
741 if (PCIE_IS_RP(bus_p))
746 } else if (PCIE_IS_PCIX(bus_p)) {
747 if (PCIE_IS_BDG(bus_p)) {
748 if (PCIX_ECC_VERSION_CHECK(bus_p)) {
758 if (PCIX_ECC_VERSION_CHECK(bus_p))
767 if (PCIE_IS_BDG(bus_p))
774 if (PCIE_IS_ROOT(bus_p)) {
864 pcie_bus_t *bus_p;
866 bus_p = (pcie_bus_t *)kmem_zalloc(sizeof (pcie_bus_t), KM_SLEEP);
867 bus_p->bus_dip = dip;
868 bus_p->bus_dev_type = PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO;
869 bus_p->bus_hdr_type = PCI_HEADER_ONE;
872 bus_p->bus_aer_off = (uint16_t)-1;
875 bus_p->bus_fm_flags |= PF_FM_READY;
877 ndi_set_bus_private(dip, B_FALSE, DEVI_PORT_TYPE_PCI, bus_p);
879 PCIE_BUS2DOM(bus_p) = PCIE_ZALLOC(pcie_domain_t);
885 pcie_bus_t *bus_p = PCIE_DIP2DOWNBUS(dip);
887 kmem_free(PCIE_BUS2DOM(bus_p), sizeof (pcie_domain_t));
888 kmem_free(bus_p, sizeof (pcie_bus_t));
964 pcie_bus_t *bus_p;
972 bus_p = kmem_zalloc(sizeof (pcie_bus_t), KM_SLEEP);
974 bus_p->bus_dip = dip;
975 bus_p->bus_bdf = bdf;
981 bus_p->bus_dev_ven_id = pci_cfgacc_get32(rcdip, bdf, PCI_CONF_VENID);
982 bus_p->bus_rev_id = pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID);
984 bus_p->bus_hdr_type = pci_cfgacc_get8(rcdip, bdf, PCI_CONF_HEADER);
985 bus_p->bus_hdr_type &= PCI_HEADER_TYPE_M;
991 bus_p->bus_dev_type = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO;
1002 switch (bus_p->bus_hdr_type) {
1014 __func__, bus_p->bus_hdr_type);
1024 bus_p->bus_pcie_off = base;
1025 bus_p->bus_dev_type = pci_cfgacc_get16(rcdip, bdf,
1029 if ((PCIE_IS_RP(bus_p) || PCIE_IS_SWD(bus_p)) &&
1034 bus_p->bus_hp_sup_modes |= PCIE_NATIVE_HP_MODE;
1039 bus_p->bus_pcix_off = base;
1040 if (PCIE_IS_BDG(bus_p))
1041 bus_p->bus_ecc_ver =
1045 bus_p->bus_ecc_ver =
1056 if (PCIE_IS_BDG(bus_p)) {
1063 bus_p->bus_pci_hp_off = base;
1064 bus_p->bus_hp_sup_modes |= PCIE_PCI_HP_MODE;
1072 if (!PCIE_IS_PCIE(bus_p))
1083 bus_p->bus_aer_off = base;
1090 if (PCIE_IS_RP(bus_p)) {
1091 bus_p->bus_rp_dip = dip;
1092 bus_p->bus_rp_bdf = bus_p->bus_bdf;
1104 bus_p->bus_rp_dip = parent_bus_p->bus_rp_dip;
1105 bus_p->bus_rp_bdf = parent_bus_p->bus_rp_bdf;
1116 bus_p->bus_rp_dip = pdip;
1117 bus_p->bus_rp_bdf = parent_bus_p->bus_bdf;
1123 bus_p->bus_soft_state = PCI_SOFT_STATE_CLOSED;
1124 bus_p->bus_fm_flags = 0;
1125 bus_p->bus_mps = 0;
1127 ndi_set_bus_private(dip, B_TRUE, DEVI_PORT_TYPE_PCI, (void *)bus_p);
1138 bus_p = PCIE_DIP2BUS(dip);
1141 if (PCIE_IS_BDG(bus_p)) {
1145 "bus-range", (caddr_t)&bus_p->bus_bus_range, &range_size)
1150 bus_p->bus_bdf, errstr);
1157 bus_p->bus_bdg_secbus = pci_cfgacc_get8(rcdip,
1158 bus_p->bus_bdf, PCI_BCNF_SECBUS);
1162 "ranges", (caddr_t)&bus_p->bus_addr_ranges,
1163 &bus_p->bus_addr_entries) != DDI_PROP_SUCCESS)
1164 bus_p->bus_addr_entries = 0;
1165 bus_p->bus_addr_entries /= sizeof (ppb_ranges_t);
1170 "assigned-addresses", (caddr_t)&bus_p->bus_assigned_addr,
1171 &bus_p->bus_assigned_entries) == DDI_PROP_SUCCESS)
1172 bus_p->bus_assigned_entries /= sizeof (pci_regspec_t);
1174 bus_p->bus_assigned_entries = 0;
1183 ddi_driver_name(dip), (void *)dip, bus_p->bus_bdf,
1184 bus_p->bus_bdg_secbus);
1186 pcie_print_bus(bus_p);
1189 return (bus_p);
1200 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
1201 ASSERT(bus_p);
1207 kmem_free(bus_p->bus_assigned_addr,
1208 (sizeof (pci_regspec_t) * bus_p->bus_assigned_entries));
1209 kmem_free(bus_p->bus_addr_ranges,
1210 (sizeof (ppb_ranges_t) * bus_p->bus_addr_entries));
1212 bus_p->bus_assigned_addr = NULL;
1213 bus_p->bus_addr_ranges = NULL;
1214 bus_p->bus_assigned_entries = 0;
1215 bus_p->bus_addr_entries = 0;
1225 kmem_free(bus_p, sizeof (pcie_bus_t));
1232 pcie_bus_t *bus_p = PCIE_DIP2BUS(cdip);
1234 if (!bus_p)
1358 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
1362 ASSERT(bus_p);
1369 if (!PCIE_IS_PCIE(bus_p))
1376 if ((reg16 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL)) !=
1384 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, tmp16);
1385 PCIE_DBG_CAP(dip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, reg16);
1389 if (PCIE_IS_ROOT(bus_p) &&
1390 (reg16 = PCIE_CAP_GET(16, bus_p, PCIE_ROOTCTL)) !=
1396 PCIE_CAP_PUT(16, bus_p, PCIE_ROOTCTL, tmp16);
1397 PCIE_DBG_CAP(dip, bus_p, "ROOT DEVCTL", 16, PCIE_ROOTCTL,
1404 if (!PCIE_HAS_AER(bus_p))
1408 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_UCE_SERV)) !=
1412 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_SERV, tmp32);
1413 PCIE_DBG_AER(dip, bus_p, "AER UCE SEV", 32, PCIE_AER_UCE_SERV,
1418 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_UCE_MASK)) !=
1422 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_MASK, tmp32);
1423 PCIE_DBG_AER(dip, bus_p, "AER UCE MASK", 32, PCIE_AER_UCE_MASK,
1428 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_CTL)) !=
1431 PCIE_AER_PUT(32, bus_p, PCIE_AER_CTL, tmp32);
1432 PCIE_DBG_AER(dip, bus_p, "AER CTL", 32, PCIE_AER_CTL, reg32);
1436 if (!PCIE_IS_PCIE_BDG(bus_p))
1440 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_SUCE_SERV)) !=
1444 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_SERV, tmp32);
1445 PCIE_DBG_AER(dip, bus_p, "AER SUCE SEV", 32, PCIE_AER_SUCE_SERV,
1449 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_SUCE_MASK)) !=
1451 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_MASK, pcie_aer_suce_mask);
1452 PCIE_DBG_AER(dip, bus_p, "AER SUCE MASK", 32,
1460 if (!PCIE_IS_ROOT(bus_p))
1463 if ((reg16 = PCIE_AER_GET(16, bus_p, PCIE_AER_RE_CMD)) !=
1465 PCIE_AER_PUT(16, bus_p, PCIE_AER_RE_CMD,
1467 PCIE_DBG_AER(dip, bus_p, "AER Root Err Cmd", 16,
1480 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
1484 if (!PCIE_IS_PCIE(bus_p))
1503 if (PCIE_HAS_AER(bus_p)) {
1505 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_MASK, tmp_pcie_aer_ce_mask);
1506 PCIE_DBG_AER(dip, bus_p, "AER CE MASK", 32, PCIE_AER_CE_MASK,
1510 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_STS, -1);
1514 if ((device_sts = PCIE_CAP_GET(16, bus_p, PCIE_DEVSTS)) !=
1516 PCIE_CAP_PUT(16, bus_p, PCIE_DEVSTS,
1520 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL);
1521 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL,
1523 PCIE_DBG_CAP(dip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, device_ctl);
1532 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
1536 if (!PCIE_IS_PCIE(bus_p))
1542 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL);
1544 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, device_ctl);
1549 if (!PCIE_HAS_AER(bus_p))
1553 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_MASK, PCIE_AER_UCE_BITS);
1556 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_MASK, PCIE_AER_CE_BITS);
1559 if ((aer_reg = PCIE_AER_GET(32, bus_p, PCIE_AER_CTL)) !=
1564 PCIE_AER_PUT(32, bus_p, PCIE_AER_CTL, aer_reg);
1569 if (!PCIE_IS_PCIE_BDG(bus_p))
1572 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_MASK, PCIE_AER_SUCE_BITS);
1578 if (!PCIE_IS_ROOT(bus_p))
1582 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_ROOTCTL);
1584 PCIE_CAP_PUT(16, bus_p, PCIE_ROOTCTL, device_ctl);
1587 if (!PCIE_HAS_AER(bus_p))
1590 if ((device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_AER_RE_CMD)) !=
1593 PCIE_CAP_PUT(16, bus_p, PCIE_AER_RE_CMD, device_ctl);
1720 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
1722 if (PCIE_IS_PCIE(bus_p)) {
1723 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) &
1738 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
1744 rp_cap = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL,
1745 bus_p->bus_pcie_off, PCIE_DEVCAP) &
1751 bus_p->bus_mps = max_supported;
1765 pcie_bus_t *bus_p;
1769 bus_p = PCIE_DIP2BUS(cdip);
1770 if (bus_p == NULL) {
1776 dev_type = bus_p->bus_dev_type;
1791 if (PCIE_IS_PCIE(bus_p)) {
1795 dev_ctrl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL);
1796 if ((fabric_mps = (PCIE_IS_RP(bus_p) ? bus_p :
1804 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, dev_ctrl);
1808 device_mps_cap = PCIE_CAP_GET(16, bus_p, PCIE_DEVCAP) &
1835 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, dev_ctrl);
1837 bus_p->bus_mps = device_mps;
2105 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
2106 bus_p->bus_pfd->pe_rber_fatal = val;
2115 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
2116 pcie_bus_t *rp_bus_p = PCIE_DIP2UPBUS(bus_p->bus_rp_dip);
2125 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
2130 if (bus_p == NULL)
2133 dev_type = bus_p->bus_dev_type;
2144 pciecap = PCIE_CAP_GET(16, bus_p, PCIE_PCIECAP);
2151 devcap2 = PCIE_CAP_GET(32, bus_p, PCIE_DEVCAP2);
2168 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
2175 devctl2 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL2);
2177 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL2, devctl2);
2189 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
2196 devctl2 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL2);
2198 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL2, devctl2);
2210 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
2217 devctl2 = PCIE_CAP_GET(32, bus_p, PCIE_DEVCTL2);
2240 * XXX - This function may be called before the bus_p structure
2243 * to populate the bus_p structures early in boot is putback.
2280 * XXX - This function may be called before the bus_p structure
2283 * to populate the bus_p structures early in boot is putback.
2328 pcie_print_bus(pcie_bus_t *bus_p)
2330 pcie_dbg("\tbus_dip = 0x%p\n", bus_p->bus_dip);
2331 pcie_dbg("\tbus_fm_flags = 0x%x\n", bus_p->bus_fm_flags);
2333 pcie_dbg("\tbus_bdf = 0x%x\n", bus_p->bus_bdf);
2334 pcie_dbg("\tbus_dev_ven_id = 0x%x\n", bus_p->bus_dev_ven_id);
2335 pcie_dbg("\tbus_rev_id = 0x%x\n", bus_p->bus_rev_id);
2336 pcie_dbg("\tbus_hdr_type = 0x%x\n", bus_p->bus_hdr_type);
2337 pcie_dbg("\tbus_dev_type = 0x%x\n", bus_p->bus_dev_type);
2338 pcie_dbg("\tbus_bdg_secbus = 0x%x\n", bus_p->bus_bdg_secbus);
2339 pcie_dbg("\tbus_pcie_off = 0x%x\n", bus_p->bus_pcie_off);
2340 pcie_dbg("\tbus_aer_off = 0x%x\n", bus_p->bus_aer_off);
2341 pcie_dbg("\tbus_pcix_off = 0x%x\n", bus_p->bus_pcix_off);
2342 pcie_dbg("\tbus_ecc_ver = 0x%x\n", bus_p->bus_ecc_ver);