Lines Matching refs:ctrl_p
73 static int pcishpc_setup_controller(pcie_hp_ctrl_t *ctrl_p);
75 static pcie_hp_slot_t *pcishpc_create_slot(pcie_hp_ctrl_t *ctrl_p);
76 static int pcishpc_register_slot(pcie_hp_ctrl_t *ctrl_p, int slot);
77 static int pcishpc_destroy_slots(pcie_hp_ctrl_t *ctrl_p);
82 static int pcishpc_issue_command(pcie_hp_ctrl_t *ctrl_p,
84 static int pcishpc_wait_busy(pcie_hp_ctrl_t *ctrl_p);
89 static void pcishpc_set_slot_name(pcie_hp_ctrl_t *ctrl_p, int slot);
100 static uint32_t pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg);
101 static void pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg,
118 static void pcishpc_dump_regs(pcie_hp_ctrl_t *ctrl_p);
137 pcie_hp_ctrl_t *ctrl_p;
143 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) != NULL) {
150 ctrl_p = pcishpc_create_controller(dip);
152 if (ctrl_p == NULL) {
157 if (pcishpc_setup_controller(ctrl_p) != DDI_SUCCESS) {
178 for (i = 0; i < ctrl_p->hc_num_slots_impl; i++) {
179 if (pcishpc_register_slot(ctrl_p, i) != DDI_SUCCESS) {
184 if (pcie_create_minor_node(ctrl_p, i) != DDI_SUCCESS) {
193 pcishpc_dump_regs(ctrl_p);
200 for (i = 0; i < ctrl_p->hc_num_slots_impl; i++) {
201 if (ctrl_p->hc_slots[i] == NULL)
204 pcie_remove_minor_node(ctrl_p, i);
219 pcie_hp_ctrl_t *ctrl_p;
224 ctrl_p = PCIE_GET_HP_CTRL(dip);
226 if (!ctrl_p) {
232 if (ctrl_p->hc_slots[i] == NULL)
235 pcie_remove_minor_node(ctrl_p, i);
238 ctrl_p->hc_flags = 0;
260 pcie_hp_ctrl_t *ctrl_p;
267 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL)
270 mutex_enter(&ctrl_p->hc_mutex);
272 if (!(ctrl_p->hc_flags & PCIE_HP_INITIALIZED_FLAG)) {
274 mutex_exit(&ctrl_p->hc_mutex);
280 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
285 ctrl_p->hc_cmd_pending = B_FALSE;
286 cv_signal(&ctrl_p->hc_cmd_comp_cv);
292 ctrl_p->hc_arbiter_timeout = B_TRUE;
296 pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
298 irq_locator = pcishpc_read_reg(ctrl_p, PCI_HP_IRQ_LOCATOR_REG);
299 irq_serr_locator = pcishpc_read_reg(ctrl_p, PCI_HP_SERR_LOCATOR_REG);
302 for (slot = 0; slot < ctrl_p->hc_num_slots_impl; slot++) {
309 reg = pcishpc_read_reg(ctrl_p,
330 if (ctrl_p->hc_slots[slot]->
332 ctrl_p->hc_slots[slot]->
336 cv_signal(&ctrl_p->hc_slots[slot]->
349 pcishpc_write_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot,
354 mutex_exit(&ctrl_p->hc_mutex);
369 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
445 mutex_enter(&ctrl_p->hc_mutex);
473 mutex_exit(&ctrl_p->hc_mutex);
475 ctrl_p->hc_dip, slot_p->hs_device_num, 0);
476 mutex_enter(&ctrl_p->hc_mutex);
557 mutex_exit(&ctrl_p->hc_mutex);
573 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
695 mutex_enter(&ctrl_p->hc_mutex);
733 mutex_exit(&ctrl_p->hc_mutex);
752 pcie_hp_ctrl_t *ctrl_p;
758 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL)
761 for (i = 0; i < PCIE_HP_MAX_SLOTS && ctrl_p->hc_slots[i]; i++) {
762 if (strcmp(ctrl_p->hc_slots[i]->hs_info.cn_name, cn_name)
765 slot_p = ctrl_p->hc_slots[i];
778 mutex_enter(&ctrl_p->hc_mutex);
785 mutex_exit(&ctrl_p->hc_mutex);
838 pcie_hp_ctrl_t *ctrl_p;
843 ctrl_p = kmem_zalloc(sizeof (pcie_hp_ctrl_t), KM_SLEEP);
844 ctrl_p->hc_dip = dip;
846 cv_init(&ctrl_p->hc_cmd_comp_cv, NULL, CV_DRIVER, NULL);
849 mutex_init(&ctrl_p->hc_mutex, NULL, MUTEX_DRIVER, NULL);
852 ctrl_p->hc_flags = PCIE_HP_INITIALIZED_FLAG;
855 PCIE_SET_HP_CTRL(dip, ctrl_p);
859 return (ctrl_p);
870 pcishpc_setup_controller(pcie_hp_ctrl_t *ctrl_p)
875 config = pcishpc_read_reg(ctrl_p, PCI_HP_SLOT_CONFIGURATION_REG);
878 ctrl_p->hc_num_slots_impl = ((config)&31);
884 ctrl_p->hc_curr_bus_speed = -1;
885 ctrl_p->hc_num_slots_connected = 0;
893 ppdip = ddi_get_parent(ddi_get_parent(ctrl_p->hc_dip));
898 ctrl_p->hc_device_start = 4;
900 ctrl_p->hc_device_start = ((config>>8)&31);
903 ctrl_p->hc_phys_start = ((config>>16)&0x7ff);
906 ctrl_p->hc_device_increases = ((config>>29)&0x1);
908 ctrl_p->hc_has_attn =
910 ctrl_p->hc_has_mrl =
913 ctrl_p->hc_cmd_pending = B_FALSE;
914 ctrl_p->hc_arbiter_timeout = B_FALSE;
916 if (ctrl_p->hc_num_slots_impl > PCIE_HP_MAX_SLOTS) {
934 pcie_hp_ctrl_t *ctrl_p;
940 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL) {
951 (void) pcishpc_destroy_slots(ctrl_p);
952 cv_destroy(&ctrl_p->hc_cmd_comp_cv);
953 mutex_destroy(&ctrl_p->hc_mutex);
954 kmem_free(ctrl_p, sizeof (pcie_hp_ctrl_t));
966 pcishpc_create_slot(pcie_hp_ctrl_t *ctrl_p)
970 PCIE_DBG("pcishpc_create_slot() called(ctrl_p=%x)\n", ctrl_p);
974 slot_p->hs_ctrl = ctrl_p;
989 pcishpc_register_slot(pcie_hp_ctrl_t *ctrl_p, int slot)
991 dev_info_t *dip = ctrl_p->hc_dip;
994 slot_p = pcishpc_create_slot(ctrl_p);
995 ctrl_p->hc_slots[slot] = slot_p;
999 if (ctrl_p->hc_device_increases)
1000 slot_p->hs_device_num = ctrl_p->hc_device_start +
1003 slot_p->hs_device_num = ctrl_p->hc_device_start -
1016 if (ctrl_p->hc_has_attn) {
1030 pcishpc_set_slot_name(ctrl_p, slot);
1057 pcishpc_destroy_slots(pcie_hp_ctrl_t *ctrl_p)
1059 dev_info_t *dip = ctrl_p->hc_dip;
1063 PCIE_DBG("pcishpc_destroy_slots() called(ctrl_p=%p)\n", ctrl_p);
1066 if ((slot_p = ctrl_p->hc_slots[i]) == NULL)
1070 mutex_enter(&ctrl_p->hc_mutex);
1075 cv_wait(&slot_p->hs_attn_btn_cv, &ctrl_p->hc_mutex);
1080 mutex_exit(&ctrl_p->hc_mutex);
1112 pcishpc_enable_irqs(pcie_hp_ctrl_t *ctrl_p)
1117 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
1122 pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
1125 for (slot = 0; slot < ctrl_p->hc_num_slots_impl; slot++) {
1126 reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);
1130 ctrl_p->hc_num_slots_connected++;
1131 if (ctrl_p->hc_curr_bus_speed == -1)
1132 ctrl_p->hc_curr_bus_speed =
1133 pcishpc_read_reg(ctrl_p,
1141 pcishpc_write_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot, reg);
1144 PCIE_DBG("pcishpc_enable_irqs: ctrl_p 0x%p, "
1145 "current bus speed 0x%x, slots connected 0x%x\n", ctrl_p,
1146 ctrl_p->hc_curr_bus_speed, ctrl_p->hc_num_slots_connected);
1158 pcishpc_disable_irqs(pcie_hp_ctrl_t *ctrl_p)
1163 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
1168 pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg);
1171 for (slot = 0; slot < ctrl_p->hc_num_slots_impl; slot++) {
1172 reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);
1177 pcishpc_write_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot, reg);
1180 PCIE_DBG("pcishpc_disable_irqs: ctrl_p 0x%p, "
1181 "current bus speed 0x%x, slots connected 0x%x\n", ctrl_p,
1182 ctrl_p->hc_curr_bus_speed, ctrl_p->hc_num_slots_connected);
1601 pcishpc_issue_command(pcie_hp_ctrl_t *ctrl_p, uint32_t cmd_code)
1605 ASSERT(MUTEX_HELD(&ctrl_p->hc_mutex));
1609 ctrl_p->hc_cmd_pending = B_TRUE;
1612 pcishpc_write_reg(ctrl_p, PCI_HP_COMMAND_STATUS_REG, cmd_code);
1614 while (ctrl_p->hc_cmd_pending == B_TRUE)
1615 cv_wait(&ctrl_p->hc_cmd_comp_cv, &ctrl_p->hc_mutex);
1618 retCode = pcishpc_wait_busy(ctrl_p);
1623 if (ctrl_p->hc_cmd_pending != B_FALSE) {
1646 pcishpc_wait_busy(pcie_hp_ctrl_t *ctrl_p)
1652 status = pcishpc_read_reg(ctrl_p, PCI_HP_COMMAND_STATUS_REG);
1880 pcishpc_set_slot_name(pcie_hp_ctrl_t *ctrl_p, int slot)
1882 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[slot];
1883 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
1894 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, ctrl_p->hc_dip,
1900 if (ctrl_p->hc_device_increases)
1901 slot_p->hs_phy_slot_num = ctrl_p->hc_phys_start + slot;
1903 slot_p->hs_phy_slot_num = ctrl_p->hc_phys_start - slot;
1905 if ((ndi_prop_update_int(DDI_DEV_T_NONE, ctrl_p->hc_dip,
1927 if (ddi_getlongprop(DDI_DEV_T_ANY, ctrl_p->hc_dip, DDI_PROP_DONTPASS,
2013 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
2014 int curr_speed = ctrl_p->hc_curr_bus_speed;
2022 status = pcishpc_read_reg(ctrl_p,
2041 if (pcishpc_issue_command(ctrl_p, ((1+slot_p->hs_num)<<8) |
2052 status = pcishpc_read_reg(ctrl_p,
2061 slots_avail1_reg = pcishpc_read_reg(ctrl_p,
2063 slots_avail2_reg = pcishpc_read_reg(ctrl_p,
2149 return ((avail_slots <= ctrl_p->hc_num_slots_connected) ?
2154 if (pcishpc_issue_command(ctrl_p, PCI_HP_COMM_STS_SET_SPEED |
2162 status = pcishpc_read_reg(ctrl_p, PCI_HP_PROF_IF_SBCR_REG) &
2173 ctrl_p->hc_curr_bus_speed = speed;
2357 pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg)
2359 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
2385 pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg, uint32_t data)
2387 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
2421 pcishpc_dump_regs(pcie_hp_ctrl_t *ctrl_p)
2434 ": 0x%08x\n", pcishpc_read_reg(ctrl_p, PCI_HP_BASE_OFFSET_REG));
2436 reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOTS_AVAIL_I_REG);
2450 reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOTS_AVAIL_II_REG);
2455 reg = pcishpc_read_reg(ctrl_p, PCI_HP_SLOT_CONFIGURATION_REG);
2477 reg = pcishpc_read_reg(ctrl_p, PCI_HP_PROF_IF_SBCR_REG);
2508 reg = pcishpc_read_reg(ctrl_p, PCI_HP_COMMAND_STATUS_REG);
2528 reg = pcishpc_read_reg(ctrl_p, PCI_HP_IRQ_LOCATOR_REG);
2538 reg = pcishpc_read_reg(ctrl_p, PCI_HP_SERR_LOCATOR_REG);
2549 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG);
2573 reg = pcishpc_read_reg(ctrl_p, PCI_HP_LOGICAL_SLOT_REGS+slot);