Lines Matching refs:ctrl_p
68 static int pciehpc_hpc_init(pcie_hp_ctrl_t *ctrl_p);
69 static int pciehpc_hpc_uninit(pcie_hp_ctrl_t *ctrl_p);
70 static int pciehpc_slotinfo_init(pcie_hp_ctrl_t *ctrl_p);
71 static int pciehpc_slotinfo_uninit(pcie_hp_ctrl_t *ctrl_p);
72 static int pciehpc_enable_intr(pcie_hp_ctrl_t *ctrl_p);
73 static int pciehpc_disable_intr(pcie_hp_ctrl_t *ctrl_p);
76 static int pciehpc_register_slot(pcie_hp_ctrl_t *ctrl_p);
77 static int pciehpc_unregister_slot(pcie_hp_ctrl_t *ctrl_p);
82 static void pciehpc_issue_hpc_command(pcie_hp_ctrl_t *ctrl_p, uint16_t control);
83 static void pciehpc_attn_btn_handler(pcie_hp_ctrl_t *ctrl_p);
85 static pcie_hp_led_state_t pciehpc_get_led_state(pcie_hp_ctrl_t *ctrl_p,
87 static void pciehpc_set_led_state(pcie_hp_ctrl_t *ctrl_p, pcie_hp_led_t led,
106 static void pciehpc_dump_hpregs(pcie_hp_ctrl_t *ctrl_p);
127 pcie_hp_ctrl_t *ctrl_p;
132 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) != NULL) {
139 ctrl_p = pciehpc_create_controller(dip);
144 ctrl_p->hc_regops = *regops;
157 ctrl_p->hc_ops.init_hpc_hw = pciehpc_hpc_init;
158 ctrl_p->hc_ops.uninit_hpc_hw = pciehpc_hpc_uninit;
159 ctrl_p->hc_ops.init_hpc_slotinfo = pciehpc_slotinfo_init;
160 ctrl_p->hc_ops.uninit_hpc_slotinfo = pciehpc_slotinfo_uninit;
161 ctrl_p->hc_ops.poweron_hpc_slot = pciehpc_slot_poweron;
162 ctrl_p->hc_ops.poweroff_hpc_slot = pciehpc_slot_poweroff;
164 ctrl_p->hc_ops.enable_hpc_intr = pciehpc_enable_intr;
165 ctrl_p->hc_ops.disable_hpc_intr = pciehpc_disable_intr;
168 pciehpc_update_ops(ctrl_p);
172 if ((ctrl_p->hc_ops.init_hpc_hw)(ctrl_p) != DDI_SUCCESS)
176 if ((ctrl_p->hc_ops.init_hpc_slotinfo)(ctrl_p) != DDI_SUCCESS)
180 if (pciehpc_register_slot(ctrl_p) != DDI_SUCCESS)
184 if (pcie_create_minor_node(ctrl_p, 0) != DDI_SUCCESS)
188 ctrl_p->hc_flags = PCIE_HP_INITIALIZED_FLAG;
192 pciehpc_dump_hpregs(ctrl_p);
197 (void) pciehpc_unregister_slot(ctrl_p);
199 (void) (ctrl_p->hc_ops.uninit_hpc_slotinfo)(ctrl_p);
202 (void) (ctrl_p->hc_ops.uninit_hpc_hw)(ctrl_p);
219 pcie_hp_ctrl_t *ctrl_p;
224 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL) {
228 pcie_remove_minor_node(ctrl_p, 0);
231 (void) pciehpc_unregister_slot(ctrl_p);
234 (void) (ctrl_p->hc_ops.uninit_hpc_slotinfo)(ctrl_p);
237 (void) (ctrl_p->hc_ops.uninit_hpc_hw)(ctrl_p);
266 pcie_hp_ctrl_t *ctrl_p;
272 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL)
275 mutex_enter(&ctrl_p->hc_mutex);
278 if (!(ctrl_p->hc_flags & PCIE_HP_INITIALIZED_FLAG)) {
279 mutex_exit(&ctrl_p->hc_mutex);
285 mutex_exit(&ctrl_p->hc_mutex);
289 slot_p = ctrl_p->hc_slots[0];
292 status = pciehpc_reg_get16(ctrl_p,
298 mutex_exit(&ctrl_p->hc_mutex);
303 pciehpc_reg_put16(ctrl_p,
310 cv_signal(&ctrl_p->hc_cmd_comp_cv);
332 control = pciehpc_reg_get16(ctrl_p,
339 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
389 control = pciehpc_reg_get16(ctrl_p,
393 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
408 if (ctrl_p->hc_dll_active_rep &&
416 mutex_exit(&ctrl_p->hc_mutex);
431 pcie_hp_ctrl_t *ctrl_p;
438 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL)
441 slot_p = ctrl_p->hc_slots[0];
504 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
505 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
510 control = pciehpc_reg_get16(ctrl_p,
517 status = pciehpc_reg_get16(ctrl_p,
558 pciehpc_set_slot_name(pcie_hp_ctrl_t *ctrl_p)
560 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
561 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
569 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, ctrl_p->hc_dip,
575 slot_capabilities = pciehpc_reg_get32(ctrl_p,
584 ddi_driver_name(ctrl_p->hc_dip),
585 ddi_get_instance(ctrl_p->hc_dip));
586 slot_p->hs_phy_slot_num = pciehpc_reg_get8(ctrl_p,
599 if (ddi_getlongprop(DDI_DEV_T_ANY, ctrl_p->hc_dip, DDI_PROP_DONTPASS,
632 pciehpc_reg_get8(pcie_hp_ctrl_t *ctrl_p, uint_t off)
634 if (ctrl_p->hc_regops.get != NULL) {
635 return ((uint8_t)ctrl_p->hc_regops.get(
636 ctrl_p->hc_regops.cookie, (off_t)off));
638 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
645 pciehpc_reg_get16(pcie_hp_ctrl_t *ctrl_p, uint_t off)
647 if (ctrl_p->hc_regops.get != NULL) {
648 return ((uint16_t)ctrl_p->hc_regops.get(
649 ctrl_p->hc_regops.cookie, (off_t)off));
651 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
658 pciehpc_reg_get32(pcie_hp_ctrl_t *ctrl_p, uint_t off)
660 if (ctrl_p->hc_regops.get != NULL) {
661 return ((uint32_t)ctrl_p->hc_regops.get(
662 ctrl_p->hc_regops.cookie, (off_t)off));
664 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
671 pciehpc_reg_put8(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint8_t val)
673 if (ctrl_p->hc_regops.put != NULL) {
674 ctrl_p->hc_regops.put(ctrl_p->hc_regops.cookie,
677 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
684 pciehpc_reg_put16(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint16_t val)
686 if (ctrl_p->hc_regops.put != NULL) {
687 ctrl_p->hc_regops.put(ctrl_p->hc_regops.cookie,
690 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
697 pciehpc_reg_put32(pcie_hp_ctrl_t *ctrl_p, uint_t off, uint32_t val)
699 if (ctrl_p->hc_regops.put != NULL) {
700 ctrl_p->hc_regops.put(ctrl_p->hc_regops.cookie,
703 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
723 pciehpc_hpc_init(pcie_hp_ctrl_t *ctrl_p)
725 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
729 reg = pciehpc_reg_get16(ctrl_p,
734 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
738 reg = pciehpc_reg_get16(ctrl_p,
740 pciehpc_reg_put16(ctrl_p,
752 pciehpc_hpc_uninit(pcie_hp_ctrl_t *ctrl_p)
755 (void) pciehpc_disable_intr(ctrl_p);
764 pciehpc_slotinfo_init(pcie_hp_ctrl_t *ctrl_p)
767 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
768 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
770 mutex_enter(&ctrl_p->hc_mutex);
777 slot_p->hs_info.cn_type_str = (ctrl_p->hc_regops.get == NULL) ?
782 PCI_MINOR_NUM(ddi_get_instance(ctrl_p->hc_dip),
787 slot_capabilities = pciehpc_reg_get32(ctrl_p,
791 pciehpc_set_slot_name(ctrl_p);
794 ctrl_p->hc_has_attn = (slot_capabilities & PCIE_SLOTCAP_ATTN_BUTTON) ?
798 ctrl_p->hc_has_mrl = (slot_capabilities & PCIE_SLOTCAP_MRL_SENSOR) ?
805 ctrl_p->hc_has_emi_lock = (slot_capabilities &
808 link_capabilities = pciehpc_reg_get32(ctrl_p,
810 ctrl_p->hc_dll_active_rep = (link_capabilities &
812 if (ctrl_p->hc_dll_active_rep)
816 if (ctrl_p->hc_has_attn) {
824 (void *)ctrl_p, 0, &p0, TS_RUN, minclsyspri);
834 mutex_exit(&ctrl_p->hc_mutex);
841 pciehpc_slotinfo_uninit(pcie_hp_ctrl_t *ctrl_p)
843 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
846 mutex_enter(&ctrl_p->hc_mutex);
851 cv_wait(&slot_p->hs_attn_btn_cv, &ctrl_p->hc_mutex);
855 mutex_exit(&ctrl_p->hc_mutex);
858 if (ctrl_p->hc_dll_active_rep)
872 pciehpc_enable_intr(pcie_hp_ctrl_t *ctrl_p)
874 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
875 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
879 reg = pciehpc_reg_get16(ctrl_p,
881 pciehpc_reg_put16(ctrl_p,
885 reg = pciehpc_reg_get16(ctrl_p,
893 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
896 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off +
908 pciehpc_disable_intr(pcie_hp_ctrl_t *ctrl_p)
910 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
914 reg = pciehpc_reg_get16(ctrl_p,
919 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off + PCIE_SLOTCTL, reg);
922 reg = pciehpc_reg_get16(ctrl_p,
924 pciehpc_reg_put16(ctrl_p,
937 pcie_hp_ctrl_t *ctrl_p;
940 ctrl_p = kmem_zalloc(sizeof (pcie_hp_ctrl_t), KM_SLEEP);
941 ctrl_p->hc_dip = dip;
944 ctrl_p->hc_slots[0] = kmem_zalloc(sizeof (pcie_hp_slot_t), KM_SLEEP);
945 ctrl_p->hc_slots[0]->hs_num = 0;
946 ctrl_p->hc_slots[0]->hs_ctrl = ctrl_p;
949 mutex_init(&ctrl_p->hc_mutex, NULL, MUTEX_DRIVER,
953 cv_init(&ctrl_p->hc_cmd_comp_cv, NULL, CV_DRIVER, NULL);
954 ctrl_p->hc_cmd_pending = B_FALSE;
957 PCIE_SET_HP_CTRL(dip, ctrl_p);
959 return (ctrl_p);
968 pcie_hp_ctrl_t *ctrl_p;
972 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL)
978 mutex_destroy(&ctrl_p->hc_mutex);
979 cv_destroy(&ctrl_p->hc_cmd_comp_cv);
980 kmem_free(ctrl_p->hc_slots[0], sizeof (pcie_hp_slot_t));
981 kmem_free(ctrl_p, sizeof (pcie_hp_ctrl_t));
988 pciehpc_register_slot(pcie_hp_ctrl_t *ctrl_p)
990 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
991 dev_info_t *dip = ctrl_p->hc_dip;
1013 pciehpc_unregister_slot(pcie_hp_ctrl_t *ctrl_p)
1015 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
1016 dev_info_t *dip = ctrl_p->hc_dip;
1045 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1046 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
1049 ASSERT(MUTEX_HELD(&ctrl_p->hc_mutex));
1065 status = pciehpc_reg_get16(ctrl_p,
1069 if ((ctrl_p->hc_has_mrl) && (status & PCIE_SLOTSTS_MRL_SENSOR_OPEN)) {
1084 control = pciehpc_reg_get16(ctrl_p,
1100 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_BLINK);
1101 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED, PCIE_HP_LED_OFF);
1104 control = pciehpc_reg_get16(ctrl_p,
1107 pciehpc_issue_hpc_command(ctrl_p, control);
1110 if (ctrl_p->hc_dll_active_rep) {
1111 status = pciehpc_reg_get16(ctrl_p,
1117 &ctrl_p->hc_mutex,
1122 status = pciehpc_reg_get16(ctrl_p,
1134 control = pciehpc_reg_get16(ctrl_p,
1145 status = pciehpc_reg_get16(ctrl_p,
1148 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off + PCIE_SLOTSTS,
1153 pciehpc_issue_hpc_command(ctrl_p, control);
1156 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_ON);
1159 if (ctrl_p->hc_has_emi_lock) {
1160 status = pciehpc_reg_get16(ctrl_p,
1164 control = pciehpc_reg_get16(ctrl_p,
1167 pciehpc_issue_hpc_command(ctrl_p, control);
1180 control = pciehpc_reg_get16(ctrl_p,
1186 pciehpc_issue_hpc_command(ctrl_p, control);
1191 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_OFF);
1201 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1202 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
1205 ASSERT(MUTEX_HELD(&ctrl_p->hc_mutex));
1222 status = pciehpc_reg_get16(ctrl_p,
1242 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_BLINK);
1245 control = pciehpc_reg_get16(ctrl_p,
1248 pciehpc_issue_hpc_command(ctrl_p, control);
1251 control = pciehpc_reg_get16(ctrl_p,
1254 pciehpc_issue_hpc_command(ctrl_p, control);
1258 control = pciehpc_reg_get16(ctrl_p,
1264 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED, PCIE_HP_LED_OFF);
1265 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED, PCIE_HP_LED_OFF);
1268 if (ctrl_p->hc_has_emi_lock) {
1269 status = pciehpc_reg_get16(ctrl_p,
1273 control = pciehpc_reg_get16(ctrl_p,
1276 pciehpc_issue_hpc_command(ctrl_p, control);
1305 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1308 mutex_enter(&ctrl_p->hc_mutex);
1316 PCIE_DISABLE_ERRORS(ctrl_p->hc_dip);
1323 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED, PCIE_HP_LED_ON);
1327 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED,
1330 mutex_exit(&ctrl_p->hc_mutex);
1334 PCIE_ENABLE_ERRORS(ctrl_p->hc_dip);
1339 mutex_exit(&ctrl_p->hc_mutex);
1354 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1357 mutex_enter(&ctrl_p->hc_mutex);
1365 PCIE_DISABLE_ERRORS(ctrl_p->hc_dip);
1373 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED,
1376 PCIE_ENABLE_ERRORS(ctrl_p->hc_dip);
1378 mutex_exit(&ctrl_p->hc_mutex);
1385 mutex_exit(&ctrl_p->hc_mutex);
1505 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1581 mutex_enter(&ctrl_p->hc_mutex);
1609 mutex_exit(&ctrl_p->hc_mutex);
1611 ctrl_p->hc_dip, slot_p->hs_device_num, 0);
1612 mutex_enter(&ctrl_p->hc_mutex);
1691 mutex_exit(&ctrl_p->hc_mutex);
1707 pcie_hp_ctrl_t *ctrl_p = slot_p->hs_ctrl;
1828 mutex_enter(&ctrl_p->hc_mutex);
1846 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED,
1866 mutex_exit(&ctrl_p->hc_mutex);
1888 pciehpc_issue_hpc_command(pcie_hp_ctrl_t *ctrl_p, uint16_t control)
1890 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
1891 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
1901 slot_cap = pciehpc_reg_get32(ctrl_p,
1910 pciehpc_reg_put16(ctrl_p,
1925 if (!(ctrl_p->hc_flags & PCIE_HP_INITIALIZED_FLAG)) {
1929 pciehpc_reg_put16(ctrl_p,
1937 status = pciehpc_reg_get16(ctrl_p,
1942 pciehpc_reg_put16(ctrl_p,
1952 ASSERT(MUTEX_HELD(&ctrl_p->hc_mutex));
1959 while (ctrl_p->hc_cmd_pending == B_TRUE)
1960 cv_wait(&ctrl_p->hc_cmd_comp_cv, &ctrl_p->hc_mutex);
1966 pciehpc_reg_put16(ctrl_p,
1969 ctrl_p->hc_cmd_pending = B_TRUE;
1971 if (cv_timedwait(&ctrl_p->hc_cmd_comp_cv, &ctrl_p->hc_mutex,
1980 status = pciehpc_reg_get16(ctrl_p,
1985 pciehpc_reg_put16(ctrl_p,
1990 ctrl_p->hc_cmd_pending = B_FALSE;
1993 cv_signal(&ctrl_p->hc_cmd_comp_cv);
2002 pciehpc_attn_btn_handler(pcie_hp_ctrl_t *ctrl_p)
2004 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
2010 CALLB_CPR_INIT(&cprinfo, &ctrl_p->hc_mutex, callb_generic_cpr,
2013 mutex_enter(&ctrl_p->hc_mutex);
2016 cv_wait(&slot_p->hs_attn_btn_cv, &ctrl_p->hc_mutex);
2021 power_led_state = pciehpc_get_led_state(ctrl_p,
2025 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED,
2030 &ctrl_p->hc_mutex,
2063 ctrl_p->hc_dip,
2069 pciehpc_set_led_state(ctrl_p, PCIE_HP_POWER_LED,
2075 cv_wait(&slot_p->hs_attn_btn_cv, &ctrl_p->hc_mutex);
2106 pciehpc_get_led_state(pcie_hp_ctrl_t *ctrl_p, pcie_hp_led_t led)
2108 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
2112 control = pciehpc_reg_get16(ctrl_p,
2144 pciehpc_set_led_state(pcie_hp_ctrl_t *ctrl_p, pcie_hp_led_t led,
2147 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
2148 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
2152 control = pciehpc_reg_get16(ctrl_p,
2204 pciehpc_issue_hpc_command(ctrl_p, control);
2208 control = pciehpc_reg_get16(ctrl_p,
2240 pcie_hp_ctrl_t *ctrl_p;
2244 if ((ctrl_p = PCIE_GET_HP_CTRL(dip)) == NULL) {
2248 slot_p = ctrl_p->hc_slots[0];
2258 mutex_enter(&ctrl_p->hc_mutex);
2259 pciehpc_set_led_state(ctrl_p, PCIE_HP_ATTN_LED,
2261 mutex_exit(&ctrl_p->hc_mutex);
2270 pciehpc_dump_hpregs(pcie_hp_ctrl_t *ctrl_p)
2272 pcie_hp_slot_t *slot_p = ctrl_p->hc_slots[0];
2273 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip);
2280 capabilities = pciehpc_reg_get32(ctrl_p,
2283 control = pciehpc_reg_get16(ctrl_p,