Lines Matching defs:nxgep
141 void nxge_virint_regs_dump(p_nxge_t nxgep);
144 nxge_virint_regs_dump(p_nxge_t nxgep)
148 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump"));
149 handle = NXGE_DEV_NPI_HANDLE(nxgep);
155 (void) npi_mac_dump_regs(handle, nxgep->function_num);
156 (void) npi_ipp_dump_regs(handle, nxgep->function_num);
158 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump"));
185 p_nxge_t nxgep;
199 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
200 if (nxgep == NULL) {
202 "nxge_cntlops: nxgep null"));
206 handle = nxgep->npi_reg_handle;
338 nxge_common_lock_get(p_nxge_t nxgep)
346 handle = nxgep->npi_reg_handle;
352 nxge_common_lock_free(p_nxge_t nxgep)
359 handle = nxgep->npi_reg_handle;
397 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token,
402 int num_ports = nxgep->nports;
413 param_arr = nxgep->param_arr;
540 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
549 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
558 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
571 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token,
576 int num_ports = nxgep->nports;
589 param_arr = nxgep->param_arr;
629 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
639 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
659 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
673 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
700 NXGE_DEBUG_MSG((nxgep,
717 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
746 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
751 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
756 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
763 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
768 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
774 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
786 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token,
791 int num_ports = nxgep->nports;
804 param_arr = nxgep->param_arr;
840 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
850 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
864 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
877 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
905 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
921 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
948 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
953 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
958 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
965 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
972 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
978 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
990 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags,
998 status = nxge_update_txdma_properties(nxgep,
1003 status = nxge_update_rxdma_properties(nxgep,
1008 status = nxge_update_rxdma_grp_properties(nxgep,
1035 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop,
1050 for (i = 0; i < nxgep->nports; i++) {
1055 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1062 for (i = 0; i < nxgep->nports; i++) {
1074 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1078 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1084 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1095 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1110 for (i = 0; i < nxgep->nports; i++) {
1115 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1131 nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg)
1137 param_arr = nxgep->param_arr;
1145 cfg_value = nxge_classify_get_cfg_value(nxgep,
1156 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[])
1165 param_arr = nxgep->param_arr;
1185 cfg_value = nxge_class_get_known_cfg(nxgep,
1187 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
1203 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
1211 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag)
1225 c_dip[num_siblings] = ddi_get_child(nxgep->p_dip);
1243 status = nxge_cfg_verify_set_classify(nxgep, c_dip);
1264 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1268 status = nxge_update_cfg_properties(nxgep,
1279 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1282 status = nxge_update_cfg_properties(nxgep,
1292 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1295 status = nxge_update_cfg_properties(nxgep,
1307 status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip);
1312 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep)
1322 param_arr = nxgep->param_arr;
1332 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0,
1334 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1341 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1346 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1353 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1369 nxge_use_cfg_link_cfg(p_nxge_t nxgep)
1387 dip = nxgep->dip;
1460 NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
1480 NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
1611 nxge_get_config_properties(p_nxge_t nxgep)
1619 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties"));
1621 if ((hw_p = nxgep->nxge_hw_p) == NULL) {
1622 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1624 " common hardware not set", nxgep->niu_type));
1631 nxgep->nports = nxge_get_nports(nxgep);
1632 if (nxgep->nports <= 0) {
1633 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1635 nxgep->niu_type));
1638 nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY;
1639 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1640 nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY;
1642 if (nxgep->function_num >= nxgep->nports) {
1646 status = nxge_get_mac_addr_properties(nxgep);
1664 switch (nxgep->niu_type) {
1666 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1671 status = nxge_cfg_verify_set(nxgep,
1673 status = nxge_cfg_verify_set(nxgep,
1678 status = nxge_use_cfg_n2niu_properties(nxgep);
1681 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1682 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1684 " unknown NIU type 0x%x", nxgep->niu_type));
1688 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1690 status = nxge_cfg_verify_set_quick_config(nxgep);
1694 status = nxge_cfg_verify_set(nxgep,
1696 status = nxge_cfg_verify_set(nxgep,
1698 status = nxge_cfg_verify_set(nxgep,
1700 status = nxge_cfg_verify_set(nxgep,
1705 nxge_use_cfg_neptune_properties(nxgep);
1716 nxgep->soft_lso_enable = ddi_prop_get_int(DDI_DEV_T_ANY, nxgep->dip,
1718 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1720 nxgep->soft_lso_enable));
1722 nxgep->niu_hw_type = NIU_HW_TYPE_DEFAULT;
1723 if (nxgep->niu_type == N2_NIU) {
1733 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1738 nxgep->niu_hw_type = NIU_HW_TYPE_RF;
1739 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1740 "NIU type %d", nxgep->niu_hw_type));
1751 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1753 nxgep->srds_prop.tx_cfg_l =
1755 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1758 nxgep->srds_prop.tx_cfg_l));
1759 nxgep->srds_prop.prop_set |= NXGE_SRDS_TXCFGL;
1762 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1764 nxgep->srds_prop.tx_cfg_h =
1766 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1769 nxgep->srds_prop.tx_cfg_h));
1770 nxgep->srds_prop.prop_set |= NXGE_SRDS_TXCFGH;
1773 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1775 nxgep->srds_prop.rx_cfg_l =
1777 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1780 nxgep->srds_prop.rx_cfg_l));
1781 nxgep->srds_prop.prop_set |= NXGE_SRDS_RXCFGL;
1784 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1786 nxgep->srds_prop.rx_cfg_h =
1788 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1791 nxgep->srds_prop.rx_cfg_h));
1792 nxgep->srds_prop.prop_set |= NXGE_SRDS_RXCFGH;
1795 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1797 nxgep->srds_prop.pll_cfg_l =
1799 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1802 nxgep->srds_prop.pll_cfg_l));
1803 nxgep->srds_prop.prop_set |= NXGE_SRDS_PLLCFGL;
1806 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1814 nxgep->phy_prop.arr =
1817 nxgep->phy_prop.cnt = tun_cnt;
1819 nxgep->phy_prop.arr[i].dev = *(uint16_t *)arr;
1821 nxgep->phy_prop.arr[i].reg = *(uint16_t *)arr;
1823 nxgep->phy_prop.arr[i].val = *(uint16_t *)arr;
1825 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1829 nxgep->phy_prop.arr[i].dev,
1830 nxgep->phy_prop.arr[i].reg,
1831 nxgep->phy_prop.arr[i].val));
1837 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties"));
1842 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep)
1846 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties"));
1848 status = nxge_use_default_dma_config_n2(nxgep);
1850 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1856 (void) nxge_use_cfg_vlan_class_config(nxgep);
1857 (void) nxge_use_cfg_mac_class_config(nxgep);
1858 (void) nxge_use_cfg_class_config(nxgep);
1859 (void) nxge_use_cfg_link_cfg(nxgep);
1865 (void) nxge_get_param_soft_properties(nxgep);
1866 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties"));
1872 nxge_use_cfg_neptune_properties(p_nxge_t nxgep)
1874 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties"));
1876 (void) nxge_use_cfg_dma_config(nxgep);
1877 (void) nxge_use_cfg_vlan_class_config(nxgep);
1878 (void) nxge_use_cfg_mac_class_config(nxgep);
1879 (void) nxge_use_cfg_class_config(nxgep);
1880 (void) nxge_use_cfg_link_cfg(nxgep);
1886 (void) nxge_get_param_soft_properties(nxgep);
1887 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties"));
1895 nxge_use_default_dma_config_n2(p_nxge_t nxgep)
1906 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2"));
1908 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1911 func = nxgep->function_num;
1914 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1919 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1930 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1935 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1941 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1950 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1956 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1961 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1972 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1977 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1983 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1990 nxgep->rdc_mask = (ndmas - 1);
1996 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2002 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2023 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2050 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2053 nxgep->function_num, i, p_cfgp->ldg[i]));
2057 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2064 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2071 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2078 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
2079 "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d",
2085 p_cfgp->max_rdc_grpids = NXGE_MAX_RDC_GROUPS / nxgep->nports;
2087 nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports;
2089 nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports;
2091 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep,
2093 NXGE_ERROR_MSG((nxgep, CFG_CTL,
2099 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2104 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2107 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip,
2111 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
2116 nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
2117 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2121 nxgep->intr_timeout = prop_val[0];
2123 nxgep->dip, "rxdma-intr-time", prop_val, prop_len);
2128 nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
2129 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2133 nxgep->intr_threshold = prop_val[0];
2135 nxgep->dip, "rxdma-intr-pkts", prop_val, prop_len);
2140 nxge_set_hw_dma_config(nxgep);
2141 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2"));
2146 nxge_use_cfg_dma_config(p_nxge_t nxgep)
2159 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config"));
2160 param_arr = nxgep->param_arr;
2162 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2164 dip = nxgep->dip;
2165 p_cfgp->function_number = nxgep->function_num;
2173 switch (nxgep->niu_type) {
2191 switch (nxgep->platform_type) {
2202 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
2205 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2216 switch (nxgep->niu_type) {
2218 tx_ndmas = tx_4_1G[nxgep->function_num];
2221 tx_ndmas = tx_2_10G[nxgep->function_num];
2225 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
2228 tx_ndmas = tx_1_10G_3_1G[nxgep->function_num];
2231 tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num];
2234 switch (nxgep->platform_type) {
2236 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
2239 tx_ndmas = p4_tx_equal[nxgep->function_num];
2244 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2250 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2260 switch (nxgep->niu_type) {
2278 switch (nxgep->platform_type) {
2289 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
2292 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2304 switch (nxgep->niu_type) {
2306 rx_ndmas = rx_4_1G[nxgep->function_num];
2309 rx_ndmas = rx_2_10G[nxgep->function_num];
2313 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
2316 rx_ndmas = rx_1_10G_3_1G[nxgep->function_num];
2319 rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num];
2322 switch (nxgep->platform_type) {
2324 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
2327 rx_ndmas = p4_rx_equal[nxgep->function_num];
2332 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2343 nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports;
2345 nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports;
2347 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep,
2349 NXGE_ERROR_MSG((nxgep, CFG_CTL,
2361 nrxgp = NXGE_MAX_RDC_GRPS / nxgep->nports;
2362 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2364 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
2374 p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS;
2377 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: "
2382 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2383 "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d "
2388 nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
2394 nxgep->intr_timeout = prop_val[0];
2396 nxgep->dip, prop, prop_val, prop_len);
2401 nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
2407 nxgep->intr_threshold = prop_val[0];
2409 nxgep->dip, prop, prop_val, prop_len);
2413 nxge_set_hw_dma_config(nxgep);
2415 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: "
2421 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config"));
2425 nxge_get_logical_props(p_nxge_t nxgep)
2427 nxge_dma_pt_cfg_t *port = &nxgep->pt_config;
2433 port->mac_port = nxgep->function_num; /* := function number */
2444 nxge_set_rdc_intr_property(nxgep);
2471 group->port = NXGE_GET_PORT_NUM(nxgep->function_num);
2478 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep)
2486 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config"));
2487 param_arr = nxgep->param_arr;
2490 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2494 nxgep->dip, prop, vlan_cfg_val, vlan_cnt);
2497 nxge_set_hw_vlan_class_config(nxgep);
2498 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config"));
2502 nxge_use_cfg_mac_class_config(p_nxge_t nxgep)
2512 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config"));
2513 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2516 param_arr = nxgep->param_arr;
2519 switch (nxgep->function_num) {
2534 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2539 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2544 nxgep->dip, prop, mac_cfg_val, mac_cnt);
2547 nxge_set_hw_mac_class_config(nxgep);
2548 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config"));
2552 nxge_use_cfg_class_config(p_nxge_t nxgep)
2554 nxge_set_hw_class_config(nxgep);
2558 nxge_set_rdc_intr_property(p_nxge_t nxgep)
2563 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property"));
2564 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2567 p_dma_cfgp->rcr_timeout[i] = nxgep->intr_timeout;
2568 p_dma_cfgp->rcr_threshold[i] = nxgep->intr_threshold;
2571 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property"));
2575 nxge_set_hw_dma_config(p_nxge_t nxgep)
2586 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config"));
2588 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2591 switch (nxgep->niu_type) {
2616 nxgep->tx_set.owned.map |= bitmap; /* Owned, & not shared. */
2617 nxgep->tx_set.owned.count = p_cfgp->tdc.owned;
2621 group = (nxge_grp_t *)nxge_grp_add(nxgep,
2645 switch (nxgep->niu_type) {
2647 nrdcs = rx_4_1G[nxgep->function_num];
2651 nrdcs = rx_2_10G[nxgep->function_num];
2654 nrdcs = rx_2_10G_2_1G[nxgep->function_num];
2657 nrdcs = rx_1_10G_3_1G[nxgep->function_num];
2660 nrdcs = rx_1_1G_1_10G_2_1G[nxgep->function_num];
2663 switch (nxgep->platform_type) {
2666 rx_2_10G_2_1G[nxgep->function_num];
2669 nrdcs = rx_4_1G[nxgep->function_num];
2697 nxgep->rx_set.owned.map |= map; /* Owned, & not shared. */
2698 nxgep->rx_set.owned.count = nrdcs;
2700 group = (nxge_grp_t *)nxge_grp_add(nxgep, NXGE_RECEIVE_GROUP);
2705 rdc_grp_p->port = NXGE_GET_PORT_NUM(nxgep->function_num);
2713 nxgep->def_rdc = p_cfgp->start_rdc;
2718 if (nxgep->function_num > 1)
2723 nxge_set_rdc_intr_property(nxgep);
2724 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config"));
2728 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc)
2734 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member"));
2736 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2742 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member"));
2747 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc)
2751 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_txdma_port_member"));
2753 if (tdc >= nxgep->pt_config.hw_config.tdc.start &&
2754 tdc < nxgep->pt_config.hw_config.tdc.count)
2757 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_txdma_port_member"));
2762 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc)
2768 NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2770 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " nxge_check_rxdma_rdcgrp_member"
2772 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2775 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " max %d ", rdc_grp_p->max_rdcs));
2779 NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2785 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp)
2791 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member"));
2793 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2798 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member"));
2803 nxge_set_hw_vlan_class_config(p_nxge_t nxgep)
2818 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config"));
2819 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2821 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2823 param_arr = nxgep->param_arr;
2844 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2853 NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2869 nxgep->dip, prop, (int *)good_cfg, good_count);
2872 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config"));
2876 nxge_set_hw_mac_class_config(p_nxge_t nxgep)
2891 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config"));
2893 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2895 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2898 param_arr = nxgep->param_arr;
2907 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2915 NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2933 nxgep->dip, prop, good_cfg, good_count);
2936 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config"));
2940 nxge_set_hw_class_config(p_nxge_t nxgep)
2952 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config"));
2954 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2955 param_arr = nxgep->param_arr;
2962 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
2975 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2986 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2995 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config"));
2999 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
3015 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2"));
3018 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3026 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
3031 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: "
3042 func = nxgep->function_num;
3046 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3051 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3062 ldgvp = nxgep->ldgvp;
3065 nxgep->ldgvp = ldgvp;
3080 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3095 ptr->nxgep = nxgep;
3096 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3122 ldvp->nxgep = nxgep;
3123 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3137 ldvp->nxgep = nxgep;
3138 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3155 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
3164 ldvp->nxgep = nxgep;
3167 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3184 sysldvp->nxgep = nxgep;
3190 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3198 set = &nxgep->rx_set;
3207 ldvp->nxgep = nxgep;
3210 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3221 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3225 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3233 set = &nxgep->tx_set;
3243 ldvp->nxgep = nxgep;
3244 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3258 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3262 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2"));
3271 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
3287 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init"));
3290 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3294 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
3303 func = nxgep->function_num;
3326 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: "
3330 ldgvp = nxgep->ldgvp;
3333 nxgep->ldgvp = ldgvp;
3344 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3357 ptr->nxgep = nxgep;
3358 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3383 set = &nxgep->rx_set;
3394 ldvp->nxgep = nxgep;
3404 set = &nxgep->tx_set;
3415 ldvp->nxgep = nxgep;
3429 ldvp->nxgep = nxgep;
3443 ldvp->nxgep = nxgep;
3447 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
3460 ldvp->nxgep = nxgep;
3465 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
3476 ldvp->nxgep = nxgep;
3483 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
3487 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init"));
3492 nxge_ldgv_uninit(p_nxge_t nxgep)
3496 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit"));
3497 ldgvp = nxgep->ldgvp;
3499 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: "
3513 nxgep->ldgvp = NULL;
3515 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit"));
3520 nxge_intr_ldgv_init(p_nxge_t nxgep)
3524 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init"));
3529 status = nxge_fzc_intr_init(nxgep);
3534 status = nxge_intr_mask_mgmt(nxgep);
3536 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init"));
3541 nxge_intr_mask_mgmt(p_nxge_t nxgep)
3550 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt"));
3552 if ((ldgvp = nxgep->ldgvp) == NULL) {
3553 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3557 handle = NXGE_DEV_NPI_HANDLE(nxgep);
3561 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3565 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3568 if (nxgep->niu_type != N2_NIU) {
3569 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3573 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3577 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3583 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3591 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3602 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
3606 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3613 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3620 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt"));
3625 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on)
3634 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3637 if (nxgep->niu_type == N2_NIU) {
3638 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3644 if ((ldgvp = nxgep->ldgvp) == NULL) {
3645 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3650 handle = NXGE_DEV_NPI_HANDLE(nxgep);
3654 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3660 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3664 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3669 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3674 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3680 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3687 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3697 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
3706 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3713 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3720 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set"));
3725 nxge_get_mac_addr_properties(p_nxge_t nxgep)
3736 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties "));
3742 (void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr);
3748 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3752 nxgep->factaddr = *(p_ether_addr_t)prop_val;
3753 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = "
3760 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3764 nxgep->ouraddr = nxgep->factaddr;
3765 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3770 nxgep->ouraddr = nxgep->factaddr;
3773 if ((!nxgep->vpd_info.present) ||
3774 (nxge_is_valid_local_mac(nxgep->factaddr)))
3777 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: "
3781 if (!nxgep->vpd_info.ver_valid) {
3782 (void) nxge_espc_mac_addrs_get(nxgep);
3783 if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3784 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
3786 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
3788 nxgep->vpd_info.ver));
3791 nxgep->ouraddr = nxgep->factaddr;
3798 nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr,
3799 nxgep->function_num, &nxgep->factaddr);
3801 if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3802 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3806 (void) nxge_espc_mac_addrs_get(nxgep);
3807 if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3808 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
3810 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
3812 nxgep->vpd_info.ver));
3817 nxgep->ouraddr = nxgep->factaddr;
3820 func_num = nxgep->function_num;
3827 nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS;
3830 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3836 nxgep->nxge_mmac_info.num_factory_mmac =
3838 if (nxgep->nxge_mmac_info.num_factory_mmac >
3840 nxgep->nxge_mmac_info.num_factory_mmac =
3844 for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) {
3846 nxgep->nxge_mmac_info.factory_mac_pool[i][j] =
3849 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3852 i, nxgep->nxge_mmac_info.factory_mac_pool[i][0],
3853 nxgep->nxge_mmac_info.factory_mac_pool[i][1],
3854 nxgep->nxge_mmac_info.factory_mac_pool[i][2],
3855 nxgep->nxge_mmac_info.factory_mac_pool[i][3],
3856 nxgep->nxge_mmac_info.factory_mac_pool[i][4],
3857 nxgep->nxge_mmac_info.factory_mac_pool[i][5]));
3871 nxgep->nxge_mmac_info.num_factory_mmac =
3872 ((nxgep->nxge_mmac_info.total_factory_macs >>
3873 (nxgep->nports >> 1))) - 1;
3877 if ((nxgep->function_num < 2) &&
3878 (nxgep->nxge_mmac_info.num_factory_mmac >
3880 nxgep->nxge_mmac_info.num_factory_mmac =
3882 } else if ((nxgep->function_num > 1) &&
3883 (nxgep->nxge_mmac_info.num_factory_mmac >
3885 nxgep->nxge_mmac_info.num_factory_mmac =
3889 for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) {
3890 (void) npi_mac_altaddr_disable(nxgep->npi_handle,
3894 (void) nxge_init_mmac(nxgep, compute_macs);
3899 nxge_get_xcvr_properties(p_nxge_t nxgep)
3904 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties"));
3909 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3910 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3914 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
3916 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3919 } else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3923 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
3925 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
4022 nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs)
4033 func_num = nxgep->function_num;
4034 base_mmac_addr = (uint16_t *)&nxgep->factaddr;
4035 mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info;
4041 if (nxgep->niu_type == N2_NIU) {
4046 (nxgep->nports - func_num) +
4082 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
4095 (void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET,
4099 nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac;
4100 nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac;
4105 * <groupid> to an index into nxgep->rx_ring_handles.
4109 nxge_get_rxring_index(p_nxge_t nxgep, int groupid, int ringidx)
4117 p_dma_cfgp = &nxgep->pt_config;
4120 if (isLDOMguest(nxgep))