Lines Matching defs:rcrp
1359 p_rx_rcr_ring_t rcrp;
1393 rcrp = (p_rx_rcr_ring_t)rcr_rings[channel],
1398 rcrp->comp_rd_index = 0;
1399 rcrp->comp_wt_index = 0;
1401 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc;
1405 rbrp, rcrp, mboxp);
1766 p_rx_rcr_ring_t rcrp;
1799 rcrp = nxgep->rx_rcr_rings->rcr_rings[ldvp->vdma_index];
1809 MUTEX_ENTER(&rcrp->lock);
1817 if (!isLDOMguest(nxgep) && (!rcrp->started)) {
1850 MUTEX_EXIT(&rcrp->lock);
1854 ASSERT(rcrp->ldgp == ldgp);
1855 ASSERT(rcrp->ldvp == ldvp);
1866 if (!rcrp->poll_flag) {
1867 mp = nxge_rx_pkts(nxgep, rcrp, cs, -1);
1883 cs.bits.hdw.mex = rcrp->poll_flag ? 0 : 1;
1890 if (rcrp->poll_flag) {
1937 MUTEX_EXIT(&rcrp->lock);
1940 mac_rx_ring(nxgep->mach, rcrp->rcr_mac_handle, mp,
1941 rcrp->rcr_gen_num);
3405 p_rx_rcr_ring_t rcrp;
3581 rcrp = (p_rx_rcr_ring_t)
3583 rcrp->rdc = dma_channel;
3586 rcrp->comp_size = nxge_port_rcr_size;
3587 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1;
3589 rcrp->max_receive_pkts = nxge_max_rx_pkts;
3591 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc;
3592 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size,
3594 rcrp->comp_rd_index = 0;
3595 rcrp->comp_wt_index = 0;
3596 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p =
3597 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc);
3599 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
3600 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
3602 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
3603 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
3606 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p +
3608 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp +
3621 rcrp->rcr_desc_rd_head_p,
3622 rcrp->rcr_desc_rd_head_pp,
3623 rcrp->rcr_desc_last_p,
3624 rcrp->rcr_desc_last_pp));
3631 rcrp->intr_timeout = (nxgep->intr_timeout <
3635 rcrp->intr_threshold = (nxgep->intr_threshold <
3639 rcrp->full_hdr_flag = B_FALSE;
3641 rcrp->sw_priv_hdr_len = nxge_rdc_buf_offset;
3644 cfga_p = &(rcrp->rcr_cfga);
3645 cfgb_p = &(rcrp->rcr_cfgb);
3648 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress;
3649 cfga_p->value = (rcrp->rcr_addr &
3653 rcfga_p->value |= ((uint64_t)rcrp->comp_size <<
3661 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold;
3662 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout;
3699 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag;
3701 switch (rcrp->sw_priv_hdr_len) {
3707 rcrp->sw_priv_hdr_len;
3715 rcrp->sw_priv_hdr_len & 0x3;
3723 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len;
3726 rbrp->rx_rcr_p = rcrp;
3727 rcrp->rx_rbr_p = rbrp;
3728 *rcr_p = rcrp;
4597 p_rx_rcr_ring_t rcrp;
4620 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[channel];
4664 rcrp->comp_rd_index = 0;
4665 rcrp->comp_wt_index = 0;
4666 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p =
4667 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc);
4669 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
4670 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
4672 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
4673 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
4676 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p +
4678 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp +
4681 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc;
4709 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp);
4735 p_rx_rcr_ring_t rcrp;
4752 rcrp = nxgep->rx_rcr_rings->rcr_rings[rdc];
4753 if (rcrp != NULL) {
4754 MUTEX_ENTER(&rcrp->lock);
4761 MUTEX_EXIT(&rcrp->lock);