Lines Matching defs:nxgep
37 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \
38 (rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid)
39 #define NXGE_ACTUAL_RDC(nxgep, rdc) \
40 (rdc + nxgep->pt_config.hw_config.start_rdc)
137 nxge_init_rxdma_channels(p_nxge_t nxgep)
139 nxge_grp_set_t *set = &nxgep->rx_set;
145 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels"));
147 if (!isLDOMguest(nxgep)) {
148 if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) {
164 nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i;
165 map = nxgep->pt_config.rdc_grps[dev_gindex].map;
168 if ((nxge_grp_dc_add(nxgep,
178 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels"));
186 nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i;
187 map = nxgep->pt_config.rdc_grps[dev_gindex].map;
190 nxge_grp_dc_remove(nxgep,
199 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels"));
245 nxge_uninit_rxdma_channels(p_nxge_t nxgep)
247 nxge_grp_set_t *set = &nxgep->rx_set;
250 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels"));
253 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
260 nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc);
264 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels"));
268 nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel)
270 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel"));
272 if (nxgep->statsp->rdc_ksp[channel]) {
273 kstat_delete(nxgep->statsp->rdc_ksp[channel]);
274 nxgep->statsp->rdc_ksp[channel] = 0;
277 nxge_rxdma_hw_stop(nxgep, channel);
278 nxge_unmap_rxdma(nxgep, channel);
280 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel"));
284 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
290 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_reset_rxdma_channel"));
292 handle = NXGE_DEV_NPI_HANDLE(nxgep);
299 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel"));
305 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep)
307 nxge_grp_set_t *set = &nxgep->rx_set;
310 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels"));
312 if (!isLDOMguest(nxgep)) {
313 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep);
317 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
318 NXGE_DEBUG_MSG((nxgep, TX_CTL,
325 NXGE_DEBUG_MSG((nxgep, RX_CTL,
333 nxgep->rx_rbr_rings->rbr_rings[rdc];
335 (void) nxge_dump_rxdma_channel(nxgep, rdc);
340 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump"));
344 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel)
350 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel"));
352 handle = NXGE_DEV_NPI_HANDLE(nxgep);
358 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel"));
363 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel,
370 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
373 handle = NXGE_DEV_NPI_HANDLE(nxgep);
383 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel,
390 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
393 handle = NXGE_DEV_NPI_HANDLE(nxgep);
409 * nxgep
426 p_nxge_t nxgep,
436 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
438 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
440 handle = NXGE_DEV_NPI_HANDLE(nxgep);
449 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp);
450 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc);
458 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
464 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc)
471 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
474 handle = NXGE_DEV_NPI_HANDLE(nxgep);
482 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
489 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel,
494 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
496 handle = NXGE_DEV_NPI_HANDLE(nxgep);
503 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold"));
508 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel,
513 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout"));
514 handle = NXGE_DEV_NPI_HANDLE(nxgep);
525 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout"));
530 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel,
538 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel"));
539 handle = NXGE_DEV_NPI_HANDLE(nxgep);
546 NXGE_DEBUG_MSG((nxgep, RX_CTL,
553 switch (nxgep->rx_bksize_code) {
586 if (isLDOMguest(nxgep)) {
594 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: "
597 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: "
602 if (nxgep->niu_hw_type == NIU_HW_TYPE_RF)
627 if (!isLDOMguest(nxgep)) {
638 if (!isLDOMguest(nxgep)) {
643 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel"));
649 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
654 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel"));
655 handle = NXGE_DEV_NPI_HANDLE(nxgep);
660 NXGE_DEBUG_MSG((nxgep, RX_CTL,
666 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel"));
671 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel)
676 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
679 handle = NXGE_DEV_NPI_HANDLE(nxgep);
682 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
699 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p,
715 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp"));
717 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
749 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
761 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
805 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
835 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
877 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
886 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
896 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
909 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
923 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
937 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index"));
943 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
959 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
974 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
980 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp"));
1056 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp)
1063 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init"));
1075 NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
1085 NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
1097 NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
1101 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init"));
1107 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p)
1116 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1153 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d",
1159 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc)
1167 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1170 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1202 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1207 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable)
1209 nxge_grp_set_t *set = &nxgep->rx_set;
1214 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
1217 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
1218 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1223 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
1224 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1231 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1239 nxgep->rx_rbr_rings->rbr_rings[rdc];
1240 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep);
1243 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
1249 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
1261 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
1268 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel)
1272 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1275 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1278 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel"));
1282 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel)
1286 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1289 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1292 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel"));
1296 nxge_hw_start_rx(p_nxge_t nxgep)
1298 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx"));
1300 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START);
1301 (void) nxge_rx_mac_enable(nxgep);
1303 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx"));
1308 nxge_fixup_rxdma_rings(p_nxge_t nxgep)
1310 nxge_grp_set_t *set = &nxgep->rx_set;
1313 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings"));
1315 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
1316 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1323 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1331 nxgep->rx_rbr_rings->rbr_rings[rdc];
1333 nxge_rxdma_hw_stop(nxgep, rdc);
1334 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1338 (void) nxge_rxdma_fix_channel(nxgep, rdc);
1343 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings"));
1347 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel)
1364 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel"));
1366 (void) nxge_rxdma_stop_channel(nxgep, channel);
1368 dma_buf_poolp = nxgep->rx_buf_pool_p;
1369 dma_cntl_poolp = nxgep->rx_cntl_pool_p;
1372 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
1379 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
1384 rx_rbr_rings = nxgep->rx_rbr_rings;
1385 rx_rcr_rings = nxgep->rx_rcr_rings;
1388 rx_mbox_areas_p = nxgep->rx_mbox_areas_p;
1404 status = nxge_rxdma_start_channel(nxgep, channel,
1410 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1415 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1420 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel)
1422 nxge_grp_set_t *set = &nxgep->rx_set;
1425 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1428 if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
1429 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1436 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1444 nxgep->rx_rbr_rings->rbr_rings[rdc];
1447 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1456 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1463 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel)
1465 nxge_grp_set_t *set = &nxgep->rx_set;
1468 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1471 if (nxgep->rx_rcr_rings == 0 || nxgep->rx_rcr_rings->rcr_rings == 0) {
1472 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1479 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1487 nxgep->rx_rcr_rings->rcr_rings[rdc];
1490 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1499 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1628 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p,
1632 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p)
1634 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page"));
1655 npi_rxdma_rdc_rbr_kick(NXGE_DEV_NPI_HANDLE(nxgep),
1658 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1662 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page"));
1751 nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p);
1761 p_nxge_t nxgep = (p_nxge_t)arg2;
1772 nxgep, ldvp));
1776 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) {
1777 nxgep = ldvp->nxgep;
1780 if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) ||
1781 (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) {
1782 NXGE_DEBUG_MSG((nxgep, INT_CTL,
1787 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1789 nxgep, ldvp));
1794 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1799 rcrp = nxgep->rx_rcr_rings->rcr_rings[ldvp->vdma_index];
1817 if (!isLDOMguest(nxgep) && (!rcrp->started)) {
1818 NXGE_DEBUG_MSG((nxgep, INT_CTL,
1836 if (isLDOMguest(nxgep)) {
1837 nxge_hio_ldgimgn(nxgep, ldgp);
1859 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d "
1867 mp = nxge_rx_pkts(nxgep, rcrp, cs, -1);
1872 (void) nxge_rx_err_evnts(nxgep, channel, cs);
1891 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
1900 if (isLDOMguest(nxgep)) {
1902 nxge_hio_ldgimgn(nxgep, ldgp);
1918 if (isLDOMguest(nxgep)) {
1919 nxge_hio_ldgimgn(nxgep, ldgp);
1933 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
1940 mac_rx_ring(nxgep->mach, rcrp->rcr_mac_handle, mp,
1943 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: DDI_INTR_CLAIMED"));
1963 nxge_rx_pkts(p_nxge_t nxgep, p_rx_rcr_ring_t rcr_p, rx_dma_ctl_stat_t cs,
1981 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_rx_pkts: "
1984 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
1987 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1990 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2003 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: "
2009 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d "
2015 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2043 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p);
2048 nxge_receive_packet(nxgep,
2076 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2104 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2108 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2128 if ((nxgep->intr_timeout != rcr_p->intr_timeout) ||
2129 (nxgep->intr_threshold != rcr_p->intr_threshold)) {
2131 rcr_p->intr_timeout = (nxgep->intr_timeout <
2133 nxgep->intr_timeout;
2135 rcr_p->intr_threshold = (nxgep->intr_threshold <
2137 nxgep->intr_threshold;
2152 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2163 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_rx_pkts: return"
2170 nxge_receive_packet(p_nxge_t nxgep,
2208 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet"));
2234 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2246 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2255 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2265 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2275 if (l2_len > nxgep->mac.maxframesize) {
2290 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2302 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2311 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2322 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p,
2327 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2334 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2340 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2345 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2352 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2360 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2365 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2370 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2375 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2419 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2438 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2446 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2469 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2480 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2485 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL,
2489 NXGE_DEBUG_MSG((nxgep, RX_CTL, " nxge_receive_packet:"
2492 nxgep->mac.maxframesize));
2508 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2519 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2536 NXGE_ERROR_MSG((nxgep,
2548 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2556 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2581 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2642 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2716 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: "
2722 NXGE_DEBUG_MSG((nxgep, RX_CTL,
2730 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
2734 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: "
2748 p_nxge_t nxgep;
2757 nxgep = ring_handle->nxgep;
2758 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index;
2759 ringp = nxgep->rx_rcr_rings->rcr_rings[channel];
2760 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2764 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2774 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2790 p_nxge_t nxgep;
2798 nxgep = ring_handle->nxgep;
2799 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index;
2800 ringp = nxgep->rx_rcr_rings->rcr_rings[channel];
2802 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2817 handle = NXGE_DEV_NPI_HANDLE(nxgep);
2842 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2847 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2851 if (isLDOMguest(nxgep)) {
2853 nxge_hio_ldgimgn(nxgep, ldgp);
2879 p_nxge_t nxgep;
2886 nxgep = ring_handle->nxgep;
2891 handle = NXGE_DEV_NPI_HANDLE(nxgep);
2892 channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index;
2893 rcr_p = nxgep->rx_rcr_rings->rcr_rings[channel];
2899 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2902 mblk = nxge_rx_pkts(nxgep, rcr_p, cs, bytes_to_pickup);
2907 (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, cs);
2912 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2920 nxge_rx_err_evnts(p_nxge_t nxgep, int channel, rx_dma_ctl_stat_t cs)
2930 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts"));
2932 handle = NXGE_DEV_NPI_HANDLE(nxgep);
2933 portn = nxgep->mac.portnum;
2934 rdc_stats = &nxgep->statsp->rdc_stats[channel];
2938 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
2941 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2946 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
2949 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2955 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
2957 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2964 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
2967 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2973 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
2976 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2982 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
2985 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2995 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3002 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
3005 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3011 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
3014 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3038 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
3041 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3047 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
3050 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3056 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
3060 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3073 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
3076 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3082 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
3085 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3091 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
3094 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3100 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3103 if (isLDOMguest(nxgep)) {
3106 status = nxge_ipp_fatal_err_recover(nxgep);
3108 FM_SERVICE_RESTORED(nxgep);
3114 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3117 if (isLDOMguest(nxgep)) {
3120 status = nxge_rxdma_fatal_err_recover(nxgep, channel);
3122 FM_SERVICE_RESTORED(nxgep);
3127 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts"));
3138 * nxgep
3153 nxge_t *nxgep, int channel)
3159 ring = nxgep->rx_rbr_rings->rbr_rings[channel];
3160 dma_common = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
3169 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: "
3175 dma_control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
3182 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: "
3196 * nxgep
3215 nxge_map_rxdma(p_nxge_t nxgep, int channel)
3226 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma"));
3228 if (!nxgep->rx_buf_pool_p) {
3229 if (nxge_alloc_rx_mem_pool(nxgep) != NXGE_OK) {
3230 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3236 if (nxge_alloc_rxb(nxgep, channel) != NXGE_OK)
3247 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
3248 rbr_ring = &nxgep->rx_rbr_rings->rbr_rings[channel];
3249 chunks = nxgep->rx_buf_pool_p->num_chunks[channel];
3251 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
3252 rcr_ring = &nxgep->rx_rcr_rings->rcr_rings[channel];
3254 mailbox = &nxgep->rx_mbox_areas_p->rxmbox_areas[channel];
3256 status = nxge_map_rxdma_channel(nxgep, channel, data, rbr_ring,
3259 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3265 nxgep->rx_rbr_rings->rbr_rings[channel]->index = (uint16_t)channel;
3266 nxgep->rx_rcr_rings->rcr_rings[channel]->index = (uint16_t)channel;
3267 nxgep->rx_rcr_rings->rcr_rings[channel]->rdc_stats =
3268 &nxgep->statsp->rdc_stats[channel];
3271 if (!isLDOMguest(nxgep))
3272 nxge_rdc_hvio_setup(nxgep, channel);
3275 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3282 nxge_unmap_rxdma(p_nxge_t nxgep, int channel)
3288 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma(%d)", channel));
3290 if (!nxgep->rx_rbr_rings || !nxgep->rx_rcr_rings ||
3291 !nxgep->rx_mbox_areas_p)
3294 rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel];
3295 rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel];
3296 mailbox = nxgep->rx_mbox_areas_p->rxmbox_areas[channel];
3302 nxgep, channel, rbr_ring, rcr_ring, mailbox);
3304 nxge_free_rxb(nxgep, channel);
3306 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma"));
3310 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel,
3322 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3327 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel,
3330 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3339 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel,
3342 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3352 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3356 nxge_unmap_rxdma_channel_cfg_ring(nxgep,
3361 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3363 "(nxgep 0x%x status 0x%x channel %d)",
3364 nxgep, status, channel));
3365 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p);
3370 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3372 "(nxgep 0x%x status 0x%x channel %d)",
3373 nxgep, status, channel));
3380 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel,
3383 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3389 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep,
3393 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p);
3395 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel"));
3400 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel,
3425 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3457 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code;
3464 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3471 rx_msg_p->nxgep = nxgep;
3559 NXGE_DEBUG_MSG((nxgep, RX_CTL,
3585 nxge_port_rcr_size = nxgep->nxge_port_rcr_size;
3611 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3631 rcrp->intr_timeout = (nxgep->intr_timeout <
3633 nxgep->intr_timeout;
3635 rcrp->intr_threshold = (nxgep->intr_threshold <
3637 nxgep->intr_threshold;
3675 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3692 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3700 if (nxgep->niu_hw_type == NIU_HW_TYPE_RF) {
3731 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3739 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep,
3742 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3749 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3754 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel,
3769 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3774 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3781 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3788 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3804 (void *)nxgep->interrupt_cookie);
3806 (void *)nxgep->interrupt_cookie);
3827 rbrp->block_size = nxgep->rx_default_block_size;
3829 if (!nxgep->mac.is_jumbo) {
3845 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3851 rbrp->block_size, nxgep->rx_default_block_size,
3873 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3884 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3895 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3916 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3929 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3938 status = nxge_rxbuf_index_info_init(nxgep, rbrp);
3939 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3952 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3974 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3982 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep,
3994 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3997 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4001 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4009 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4020 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4028 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4057 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4070 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4076 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4084 * nxgep
4098 nxge_rxdma_hw_start_common(p_nxge_t nxgep)
4102 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common"));
4109 (void) nxge_init_fzc_rx_common(nxgep);
4115 (void) nxge_init_fzc_rxdma_port(nxgep);
4117 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common"));
4123 nxge_rxdma_hw_start(p_nxge_t nxgep, int channel)
4134 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start"));
4136 rx_rbr_rings = nxgep->rx_rbr_rings;
4137 rx_rcr_rings = nxgep->rx_rcr_rings;
4139 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4145 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4150 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4155 rx_mbox_areas_p = nxgep->rx_mbox_areas_p;
4161 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4164 status = nxge_rxdma_start_channel(nxgep, channel,
4169 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4175 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: "
4179 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4186 nxge_rxdma_hw_stop(p_nxge_t nxgep, int channel)
4191 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop"));
4193 rx_rbr_rings = nxgep->rx_rbr_rings;
4194 rx_rcr_rings = nxgep->rx_rcr_rings;
4196 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4201 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4204 (void) nxge_rxdma_stop_channel(nxgep, channel);
4206 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: "
4210 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop"));
4215 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel,
4225 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel"));
4227 handle = NXGE_DEV_NPI_HANDLE(nxgep);
4229 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: "
4231 nxgep->npi_handle.regp, nxgep->npi_handle.regh));
4234 if (!isLDOMguest(nxgep)) {
4237 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4244 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4250 if (isLDOMguest(nxgep))
4251 (void) nxge_rdc_lp_conf(nxgep, channel);
4259 if (!isLDOMguest(nxgep)) {
4260 status = nxge_init_fzc_rxdma_channel(nxgep, channel);
4262 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4269 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4279 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4287 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4298 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs);
4299 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: "
4302 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4309 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: "
4317 status = nxge_enable_rxdma_channel(nxgep,
4321 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4328 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4331 if (isLDOMguest(nxgep)) {
4333 status = nxge_hio_intr_add(nxgep, VP_BOUND_RX, channel);
4335 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4349 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4356 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: "
4359 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel"));
4365 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel)
4373 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel"));
4375 handle = NXGE_DEV_NPI_HANDLE(nxgep);
4377 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: "
4379 nxgep->npi_handle.regp, nxgep->npi_handle.regh));
4381 if (!isLDOMguest(nxgep)) {
4385 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) {
4386 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4394 (void) nxge_ipp_drain(nxgep);
4400 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4407 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4415 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4422 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4429 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs);
4430 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control "
4433 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4440 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4446 status = nxge_disable_rxdma_channel(nxgep, channel);
4449 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4456 if (!isLDOMguest(nxgep)) {
4460 if (nxge_rx_mac_enable(nxgep) != NXGE_OK) {
4461 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4466 NXGE_DEBUG_MSG((nxgep,
4469 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel"));
4475 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep)
4486 handle = nxgep->npi_handle;
4487 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats;
4496 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL,
4502 switch (nxgep->mac.portnum) {
4541 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status,
4551 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status,
4559 portn = nxgep->mac.portnum;
4560 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats;
4564 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
4571 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL,
4577 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4581 status = nxge_rx_port_fatal_err_recover(nxgep);
4583 FM_SERVICE_RESTORED(nxgep);
4591 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel)
4606 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover"));
4607 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4616 handle = NXGE_DEV_NPI_HANDLE(nxgep);
4617 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop..."));
4619 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[channel];
4620 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[channel];
4625 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel..."));
4629 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4634 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt..."));
4640 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4646 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset..."));
4651 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4657 nxge_port_rcr_size = nxgep->nxge_port_rcr_size;
4659 mboxp = (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[channel];
4692 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4707 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start..."));
4709 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp);
4717 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4720 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover"));
4726 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed"));
4731 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep)
4733 nxge_grp_set_t *set = &nxgep->rx_set;
4738 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover"));
4739 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4741 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disabling RxMAC...\n"));
4743 if (nxge_rx_mac_disable(nxgep) != NXGE_OK)
4748 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stopping all RxDMA channels..."));
4752 rcrp = nxgep->rx_rcr_rings->rcr_rings[rdc];
4755 if (nxge_rxdma_fatal_err_recover(nxgep,
4757 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4766 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Resetting IPP..."));
4769 if (nxge_ipp_reset(nxgep) != NXGE_OK) {
4770 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4776 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC..."));
4779 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) {
4780 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4786 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP..."));
4789 if (nxge_ipp_init(nxgep) != NXGE_OK) {
4790 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4796 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC..."));
4799 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) {
4800 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4806 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC..."));
4809 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) {
4810 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4816 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4821 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed"));
4826 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan)
4846 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG,
4883 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG,
4891 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum);
4893 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum);
4895 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum);
4905 NXGE_REG_WR64(nxgep->npi_handle,