Lines Matching refs:nxgep
544 nxge_get_param_soft_properties(p_nxge_t nxgep)
553 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties"));
555 param_arr = nxgep->param_arr;
556 param_count = nxgep->param_count;
565 nxgep->dip, 0, param_arr[i].fcode_name,
591 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
600 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
602 nxgep->instance));
603 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
612 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
621 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
623 nxgep->instance));
624 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
636 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr)
645 NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
660 return (nxge_check_rdcgrp_port_member(nxgep, grp));
675 NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
678 return (nxge_check_txdma_port_member(nxgep, channel));
684 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register"));
690 nxge_setup_param(p_nxge_t nxgep)
696 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param"));
702 nxge_param_arr[param_instance].value = nxgep->instance;
704 param_arr = nxgep->param_arr;
705 param_arr[param_instance].value = nxgep->instance;
706 param_arr[param_function_number].value = nxgep->function_num;
708 for (i = 0; i < nxgep->param_count; i++) {
710 (nxge_private_param_register(nxgep,
731 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param"));
735 nxge_init_param(p_nxge_t nxgep)
740 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param"));
745 nxge_param_arr[param_instance].value = nxgep->instance;
747 param_arr = nxgep->param_arr;
778 nxgep->param_arr = param_arr;
779 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t);
781 nxge_param_sync(nxgep);
783 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d",
784 nxgep->param_count));
788 nxge_destroy_param(p_nxge_t nxgep)
793 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param"));
795 if (nxgep->param_arr == NULL)
800 if (nxge_param_arr[param_instance].value == nxgep->instance) {
803 (i != nxgep->instance))
809 for (i = 0; i < nxgep->param_count; i++)
810 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
811 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
812 free_count = ((nxgep->param_arr[i].type &
818 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value,
821 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size);
825 nxgep->param_arr[i].old_value, free_size);
827 KMEM_FREE((void *)nxgep->param_arr[i].old_value,
832 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr));
833 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param"));
843 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
847 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
856 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic"));
862 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
866 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac"));
869 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac"));
875 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
877 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver"));
880 nxgep->instance, nxgep->vpd_info.ver);
882 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver"));
888 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
890 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode"));
892 switch (nxgep->mac.portmode) {
895 nxgep->instance,
896 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
900 nxgep->instance,
901 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
905 "%s\n", nxgep->instance,
906 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
910 nxgep->instance,
911 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
915 "%s\n", nxgep->instance,
916 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
920 nxgep->instance,
921 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
925 "Fiber %s\n", nxgep->instance,
926 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
930 "PHY, Currently NOT present\n", nxgep->instance);
934 " 10G Copper with TN1010 %s\n", nxgep->instance,
935 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
939 " 1G Copper with TN1010 %s\n", nxgep->instance,
940 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
944 nxgep->instance,
945 nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
950 nxgep->instance,
951 nxgep->soft_lso_enable ? "enable" : "disable");
953 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode"));
959 nxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
963 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time"));
965 pa->value = (uint32_t)nxgep->intr_timeout;
966 (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout);
968 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time"));
974 nxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
978 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts"));
980 pa->value = (uint32_t)nxgep->intr_threshold;
981 (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold);
983 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts"));
989 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
1000 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info"));
1003 nxgep->function_num);
1019 set = &nxgep->tx_set;
1029 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info"));
1035 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
1049 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info"));
1052 nxgep->function_num);
1062 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1065 rx_rcr_rings = nxgep->rx_rcr_rings;
1067 rx_rbr_rings = nxgep->rx_rbr_rings;
1082 set = &nxgep->rx_set;
1098 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info"));
1104 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q,
1115 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1118 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1122 nxgep->function_num);
1189 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1216 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1223 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic"));
1230 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic"));
1237 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1240 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance"));
1241 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance"));
1248 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1256 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac"));
1267 if (!nxge_param_link_update(nxgep)) {
1268 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1273 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac"));
1279 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1286 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts"));
1298 nxgep->intr_threshold = pa->value;
1301 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts"));
1307 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1314 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time"));
1326 nxgep->intr_timeout = pa->value;
1329 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time"));
1335 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1349 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp "));
1351 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1353 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1361 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x",
1366 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1395 status = nxge_logical_mac_assign_rdc_table(nxgep,
1401 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp"));
1407 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1423 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1425 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1427 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1450 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1486 NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
1505 NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
1515 status = nxge_fflp_config_vlan_table(nxgep,
1521 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp"));
1527 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1545 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1547 nxgep->function_num);
1554 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1563 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1593 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp"));
1599 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1611 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp "));
1614 nxgep->function_num);
1623 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1624 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1649 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp"));
1655 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q,
1663 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable"));
1674 status = nxge_fflp_config_tcam_enable(nxgep);
1676 status = nxge_fflp_config_tcam_disable(nxgep);
1681 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable"));
1687 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q,
1695 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable"));
1706 status = nxge_fflp_config_hash_lookup_enable(nxgep);
1708 status = nxge_fflp_config_hash_lookup_disable(nxgep);
1713 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable"));
1719 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q,
1727 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable"));
1738 status = nxge_fflp_config_tcam_enable(nxgep);
1740 status = nxge_fflp_config_tcam_disable(nxgep);
1745 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable"));
1751 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q,
1760 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr"));
1779 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr"));
1782 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr"));
1788 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q,
1797 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr"));
1813 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value);
1816 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr"));
1822 nxge_class_name_2value(p_nxge_t nxgep, char *name)
1828 param_arr = nxgep->param_arr;
1839 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q,
1848 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt"));
1863 class = nxge_class_name_2value(nxgep, pa->name);
1874 status = nxge_fflp_ip_class_config(nxgep, class, pa->value);
1879 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt"));
1885 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q,
1892 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt"));
1895 class = nxge_class_name_2value(nxgep, pa->name);
1900 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
1910 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1916 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));
1922 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q,
1931 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init"));
1938 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1956 status = nxge_fflp_set_hash1(nxgep,
1960 status = nxge_fflp_set_hash2(nxgep,
1965 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1975 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init"));
1981 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q,
1994 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1997 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc"));
2021 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp,
2024 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2030 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp,
2036 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc"));
2042 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q,
2053 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc"));
2054 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2072 if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0)
2074 status = nxge_rxdma_cfg_port_default_rdc(nxgep,
2075 nxgep->function_num, rdc);
2080 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc"));
2086 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q,
2095 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag"));
2099 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2111 nxgep->nxge_debug_level = pa->value;
2114 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag"));
2120 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2125 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag"));
2133 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag"));
2139 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q,
2148 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag"));
2152 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag"
2165 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag"));
2171 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2173 nxge_grp_set_t *set = &nxgep->rx_set;
2176 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc"));
2178 if (!isLDOMguest(nxgep))
2179 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep));
2183 (void) nxge_dump_rxdma_channel(nxgep, rdc);
2187 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc"));
2193 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2195 nxge_grp_set_t *set = &nxgep->tx_set;
2198 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc"));
2202 (void) nxge_txdma_regs_dump(nxgep, tdc);
2206 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc"));
2212 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2214 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs"));
2216 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep));
2218 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs"));
2224 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2226 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs"));
2228 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
2229 nxgep->function_num);
2231 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs"));
2237 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2239 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs"));
2241 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
2242 nxgep->function_num);
2243 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs"));
2249 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2251 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table"));
2253 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep));
2255 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table"));
2261 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2265 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table"));
2267 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep),
2271 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table"));
2304 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2319 NXGE_DEBUG_MSG((nxgep, IOC_CTL,
2323 nxgep->function_num);
2333 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2336 rx_rcr_rings = nxgep->rx_rcr_rings;
2338 rx_rbr_rings = nxgep->rx_rbr_rings;
2341 "nxgep (nxge_t) $%p\n"
2343 (void *)nxgep, (void *)nxgep->dev_regs);
2351 (void *)nxgep->dev_regs->nxge_regp,
2352 (void *)nxgep->dev_regs->nxge_pciregp);
2362 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp;
2364 base = (uint64_t)nxgep->dev_regs->nxge_regp;
2393 tx_rings = nxgep->tx_rings->rings;
2403 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs"));
2410 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param)
2449 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data)
2456 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value,
2463 nxge_param_link_update(p_nxge_t nxgep)
2472 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update"));
2474 param_arr = nxgep->param_arr;
2475 instance = nxgep->instance;
2489 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2491 RW_ENTER_WRITER(&nxgep->filter_lock);
2492 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
2493 (void) nxge_link_init(nxgep);
2494 (void) nxge_mac_init(nxgep);
2495 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
2496 RW_EXIT(&nxgep->filter_lock);
2509 RW_ENTER_WRITER(&nxgep->filter_lock);
2510 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2512 (void) nxge_rx_mac_disable(nxgep);
2513 (void) nxge_tx_mac_disable(nxgep);
2514 (void) nxge_tx_mac_enable(nxgep);
2515 (void) nxge_rx_mac_enable(nxgep);
2516 RW_EXIT(&nxgep->filter_lock);
2520 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2534 nxge_param_sync(p_nxge_t nxgep)
2537 param_arr = nxgep->param_arr;
2539 nxgep->param_en_pause = param_arr[param_anar_pause].value;
2540 nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value;
2541 nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value;
2542 nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value;
2547 nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp)
2553 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt"));
2556 class = nxge_class_name_2value(nxgep, pa->name);
2561 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
2571 NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2576 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));