Lines Matching +defs:val +defs:channel
834 /* Find our VR & channel sets. */
1635 * enable the port, configure the dma channel bitmap,
2289 * Assume that each DMA channel will be configured with
2436 * channel The channel to map into our kernel space.
2456 int channel)
2479 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
2480 num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel];
2483 nxgep, channel, data, rx_buf_alloc_size,
2489 "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data));
2494 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
2497 nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size))
2514 int channel)
2522 data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
2523 num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel];
2526 nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0;
2527 nxgep->rx_buf_pool_p->num_chunks[channel] = 0;
2529 control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
2532 nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0;
2715 "==> nxge_alloc_rx_buf_dma: not enough for channel %d "
2724 "==> nxge_alloc_rx_buf_dma: Allocated for channel %d "
2840 * Assume that each DMA channel will be configured with the
2888 * channel The channel to map into our kernel space.
2908 int channel)
2927 dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel];
2928 num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel];
2930 dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel];
2944 status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p,
2954 status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p,
2968 int channel)
2976 data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel];
2977 num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel];
2980 nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0;
2981 nxgep->tx_buf_pool_p->num_chunks[channel] = 0;
2983 control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel];
2986 nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0;
2998 * The per-channel (TDC) data structures are allocated when needed.
3025 * Allocate memory for each transmit DMA channel.
3162 "==> nxge_alloc_tx_buf_dma: not enough channel %d: "
3171 "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: "
3268 * The per-channel (TDC) data structures are freed when the channel
4713 uint64_t val = statsp->mac_stats.link_speed * 1000000ull;
4715 ASSERT(pr_valsize >= sizeof (val));
4716 bcopy(&val, pr_val, sizeof (val));
5541 uint32_t channel;
5544 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index;
5545 ring = nxgep->tx_rings->rings[channel];
5560 uint32_t channel;
5563 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index;
5564 ring = nxgep->tx_rings->rings[channel];
5577 uint32_t channel;
5581 channel = nxgep->pt_config.hw_config.start_rdc + rhp->index;
5582 ring = nxgep->rx_rcr_rings->rcr_rings[channel];
5595 (nxgep->ldgvp->ldvp[i].channel == channel)) {
5615 uint32_t channel;
5618 channel = nxgep->pt_config.hw_config.start_rdc + rhp->index;
5619 ring = nxgep->rx_rcr_rings->rcr_rings[channel];
5631 nxge_ring_get_htable_idx(p_nxge_t nxgep, mac_ring_type_t type, uint32_t channel)
5639 channel));
5649 (nxgep->ldgvp->ldvp[i].channel == channel)) {
5659 (nxgep->ldgvp->ldvp[i].channel == channel)) {
5679 uint32_t channel;
5705 channel = nxgep->pt_config.hw_config.tdc.start + index;
5706 rhandlep->channel = channel;
5709 channel);
5740 channel = nxgep->pt_config.hw_config.start_rdc + index;
5748 rhandlep->channel = channel;
5760 channel);
5792 uint16_t channel; /* device-wise ring id */
5801 * nxge_grp_dc_add takes a channel number which is a
5804 channel = nxge->pt_config.hw_config.tdc.start + rhandle->index;
5810 (void) nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel);
5818 rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel);
5837 * nxge_grp_dc_add takes a channel number which is a
5840 channel = nxge->pt_config.hw_config.start_rdc + rhandle->index;
5841 rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_RX, channel);
5847 rdc_grp->map |= (1 << channel);
5862 uint16_t channel; /* device-wise ring id */
5872 channel = nxge->pt_config.hw_config.tdc.start + rhandle->index;
5873 nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel);
5881 (void) nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel);
5889 channel = rdc_grp->start_rdc + rhandle->index;
5890 nxge_grp_dc_remove(nxge, VP_BOUND_RX, channel);
5892 rdc_grp->map &= ~(1 << channel);
6753 " property[%d] val[%s]",