Lines Matching defs:nxgep
215 static nxge_status_t nxge_map_regs(p_nxge_t nxgep);
216 static void nxge_unmap_regs(p_nxge_t nxgep);
218 static void nxge_test_map_regs(p_nxge_t nxgep);
221 static nxge_status_t nxge_add_intrs(p_nxge_t nxgep);
222 static void nxge_remove_intrs(p_nxge_t nxgep);
224 static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep);
227 static void nxge_intrs_enable(p_nxge_t nxgep);
228 static void nxge_intrs_disable(p_nxge_t nxgep);
275 extern nxge_status_t nxge_hio_rdc_enable(p_nxge_t nxgep);
288 static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr,
290 void nxge_mmac_kstat_update(p_nxge_t nxgep, int slot,
312 static void nxge_niu_peu_reset(p_nxge_t nxgep);
536 p_nxge_t nxgep = NULL;
542 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach"));
552 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH"));
556 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME"));
557 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
558 if (nxgep == NULL) {
562 if (nxgep->dip != dip) {
566 if (nxgep->suspended == DDI_PM_SUSPEND) {
567 status = ddi_dev_is_needed(nxgep->dip, 0, 1);
569 status = nxge_resume(nxgep);
574 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME"));
575 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
576 if (nxgep == NULL) {
580 if (nxgep->dip != dip) {
584 status = nxge_resume(nxgep);
588 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown"));
599 nxgep = ddi_get_soft_state(nxge_list, instance);
600 if (nxgep == NULL) {
605 nxgep->nxge_magic = NXGE_MAGIC;
607 nxgep->drv_state = 0;
608 nxgep->dip = dip;
609 nxgep->instance = instance;
610 nxgep->p_dip = ddi_get_parent(dip);
611 nxgep->nxge_debug_level = nxge_debug_level;
615 nxge_get_environs(nxgep);
617 status = nxge_map_regs(nxgep);
620 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed"));
624 nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, &nxge_rx_dma_attr);
628 status = nxge_init_common_dev(nxgep);
630 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
638 if (nxgep->niu_type != N2_NIU) {
639 nxge_set_pci_replay_timeout(nxgep);
644 if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS)
648 if ((status = nxge_hio_init(nxgep)) != NXGE_OK) {
649 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
654 if (nxgep->niu_type == NEPTUNE_2_10GF) {
655 if (nxgep->function_num > 1) {
656 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported"
658 "supported for this card.", nxgep->function_num));
664 if (isLDOMguest(nxgep)) {
668 nxgep->mac.portnum = nxgep->function_num;
669 nxgep->mac.porttype = PORT_TYPE_LOGICAL;
672 mmac_info = &nxgep->nxge_mmac_info;
676 portn = NXGE_GET_PORT_NUM(nxgep->function_num);
677 nxgep->mac.portnum = portn;
679 nxgep->mac.porttype = PORT_TYPE_XMAC;
681 nxgep->mac.porttype = PORT_TYPE_BMAC;
687 mmac_info = &nxgep->nxge_mmac_info;
688 if (nxgep->function_num < 2) {
699 nxge_init_param(nxgep);
707 nxge_init_statsp(nxgep);
713 if (!isLDOMguest(nxgep)) {
718 nxge_vpd_info_get(nxgep);
722 ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS,
733 nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF;
740 nxge_hw_id_init(nxgep);
742 if (isLDOMguest(nxgep)) {
749 nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR;
750 nxgep->mac.portmode = PORT_LOGICAL;
751 (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip,
754 nxgep->nports = 1;
755 nxgep->board_ver = 0; /* XXX What? */
762 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
771 ether_copy(prop_val, nxgep->hio_mac_addr);
773 nxge_get_logical_props(nxgep);
780 nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
784 nxgep->mac.is_jumbo = B_TRUE;
785 nxgep->mac.maxframesize = (uint16_t)max_frame_size;
786 nxgep->mac.default_mtu = nxgep->mac.maxframesize -
790 status = nxge_xcvr_find(nxgep);
793 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: "
799 status = nxge_get_config_properties(nxgep);
802 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
811 nxge_setup_kstats(nxgep);
813 if (!isLDOMguest(nxgep))
814 nxge_setup_param(nxgep);
816 status = nxge_setup_system_dma_pages(nxgep);
818 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed"));
823 if (!isLDOMguest(nxgep))
824 nxge_hw_init_niu_common(nxgep);
826 status = nxge_setup_mutexes(nxgep);
828 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed"));
833 if (isLDOMguest(nxgep)) {
835 status = nxge_hio_vr_add(nxgep);
837 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
839 (void) hsvc_unregister(&nxgep->niu_hsvc);
840 nxgep->niu_hsvc_available = B_FALSE;
847 status = nxge_setup_dev(nxgep);
849 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed"));
853 status = nxge_add_intrs(nxgep);
855 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed"));
860 if ((status = nxge_mac_register(nxgep)) != NXGE_OK) {
861 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
866 mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN);
868 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
872 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
877 nxge_unattach(nxgep);
884 nxge_destroy_param(nxgep);
889 nxge_destroy_kstats(nxgep);
892 if (nxgep->nxge_hw_p) {
893 nxge_uninit_common_dev(nxgep);
894 nxgep->nxge_hw_p = NULL;
901 nxge_unmap_regs(nxgep);
903 nxge_fm_fini(nxgep);
906 ddi_soft_state_free(nxge_list, nxgep->instance);
911 nxgep = NULL;
914 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x",
925 p_nxge_t nxgep = NULL;
927 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach"));
929 nxgep = ddi_get_soft_state(nxge_list, instance);
930 if (nxgep == NULL) {
937 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH"));
941 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND"));
942 nxgep->suspended = DDI_PM_SUSPEND;
943 nxge_suspend(nxgep);
947 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND"));
948 if (nxgep->suspended != DDI_PM_SUSPEND) {
949 nxgep->suspended = DDI_SUSPEND;
950 nxge_suspend(nxgep);
964 nxgep->suspended = cmd;
966 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
968 if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) {
969 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
974 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
977 nxge_unattach(nxgep);
978 nxgep = NULL;
981 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X",
988 nxge_unattach(p_nxge_t nxgep)
990 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach"));
992 if (nxgep == NULL || nxgep->dev_regs == NULL) {
996 nxgep->nxge_magic = 0;
998 if (nxgep->nxge_timerid) {
999 nxge_stop_timer(nxgep, nxgep->nxge_timerid);
1000 nxgep->nxge_timerid = 0;
1007 if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) {
1008 nxge_niu_peu_reset(nxgep);
1012 if (isLDOMguest(nxgep)) {
1013 (void) nxge_hio_vr_release(nxgep);
1017 if (nxgep->nxge_hw_p) {
1018 nxge_uninit_common_dev(nxgep);
1019 nxgep->nxge_hw_p = NULL;
1023 if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) {
1024 (void) hsvc_unregister(&nxgep->niu_hsvc);
1025 nxgep->niu_hsvc_available = B_FALSE;
1031 nxge_remove_intrs(nxgep);
1036 if (!isLDOMguest(nxgep)) {
1037 nxge_destroy_dev(nxgep);
1043 nxge_destroy_param(nxgep);
1048 nxge_destroy_kstats(nxgep);
1053 if (nxgep->phy_prop.cnt > 0) {
1054 KMEM_FREE(nxgep->phy_prop.arr,
1055 sizeof (nxge_phy_mdio_val_t) * nxgep->phy_prop.cnt);
1056 nxgep->phy_prop.cnt = 0;
1062 nxge_destroy_mutexes(nxgep);
1068 if (nxgep->dip) {
1069 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1072 (void) ddi_prop_remove_all(nxgep->dip);
1076 nxge_remove_hard_properties(nxgep);
1082 nxge_unmap_regs(nxgep);
1084 nxge_fm_fini(nxgep);
1086 ddi_soft_state_free(nxge_list, nxgep->instance);
1093 nxge_hsvc_register(nxge_t *nxgep)
1098 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hsvc_register"));
1099 if (nxgep->niu_type != N2_NIU) {
1100 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hsvc_register"));
1110 nxgep->niu_hsvc_available = B_FALSE;
1111 bcopy(&niu_hsvc, &nxgep->niu_hsvc,
1115 nxgep->niu_hsvc.hsvc_major = i;
1117 nxgep->niu_hsvc.hsvc_minor = j;
1118 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1123 nxgep->niu_hsvc.hsvc_modname,
1124 nxgep->niu_hsvc.hsvc_rev,
1125 nxgep->niu_hsvc.hsvc_group,
1126 nxgep->niu_hsvc.hsvc_major,
1127 nxgep->niu_hsvc.hsvc_minor,
1128 nxgep->niu_min_ver));
1130 if ((status = hsvc_register(&nxgep->niu_hsvc,
1131 &nxgep->niu_min_ver)) == 0) {
1133 nxgep->niu_hsvc.hsvc_minor = nxgep->niu_min_ver;
1134 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1139 nxgep->niu_hsvc.hsvc_modname,
1140 nxgep->niu_hsvc.hsvc_rev,
1141 nxgep->niu_hsvc.hsvc_group,
1142 nxgep->niu_hsvc.hsvc_major,
1143 nxgep->niu_hsvc.hsvc_minor,
1144 nxgep->niu_min_ver));
1146 nxgep->niu_hsvc_available = B_TRUE;
1147 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1153 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1159 nxgep->niu_hsvc.hsvc_modname,
1160 nxgep->niu_hsvc.hsvc_rev,
1161 nxgep->niu_hsvc.hsvc_group,
1162 nxgep->niu_hsvc.hsvc_major,
1163 nxgep->niu_hsvc.hsvc_minor, status));
1167 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1175 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1185 nxge_map_regs(p_nxge_t nxgep)
1201 if (isLDOMguest(nxgep)) {
1202 return (nxge_guest_regs_map(nxgep));
1205 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs"));
1206 nxgep->dev_regs = NULL;
1213 nxgep->niu_type = NIU_TYPE_NONE;
1215 devname = ddi_pathname(nxgep->dip, buf);
1217 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1226 nxgep->niu_type = N2_NIU;
1227 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1233 nxgep->function_num =
1235 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1237 nxgep->function_num));
1243 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
1246 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1253 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1256 nxgep->function_num = func_num;
1257 if (isLDOMguest(nxgep)) {
1258 nxgep->function_num /= 2;
1265 switch (nxgep->niu_type) {
1267 (void) ddi_dev_regsize(nxgep->dip, 0, ®size);
1268 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1271 ddi_status = ddi_regs_map_setup(nxgep->dip, 0,
1275 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1279 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1300 (void) ddi_dev_regsize(nxgep->dip, 1, ®size);
1301 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1304 ddi_status = ddi_regs_map_setup(nxgep->dip, 1,
1308 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1314 (void) ddi_dev_regsize(nxgep->dip, 2, ®size);
1315 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1317 ddi_status = ddi_regs_map_setup(nxgep->dip, 2,
1321 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1327 (void) ddi_dev_regsize(nxgep->dip, 3, ®size);
1328 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1330 ddi_status = ddi_regs_map_setup(nxgep->dip, 3,
1335 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1339 nxgep->dev_regs = dev_regs;
1341 NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh);
1342 NPI_PCI_ADD_HANDLE_SET(nxgep,
1344 NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh);
1345 NPI_MSI_ADD_HANDLE_SET(nxgep,
1348 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh);
1349 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp);
1351 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh);
1352 NPI_REG_ADD_HANDLE_SET(nxgep,
1355 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh);
1356 NPI_VREG_ADD_HANDLE_SET(nxgep,
1362 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU"));
1367 (void) ddi_dev_regsize(nxgep->dip, 1, ®size);
1368 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1370 ddi_status = ddi_regs_map_setup(nxgep->dip, 1,
1375 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1381 (void) ddi_dev_regsize(nxgep->dip, 2, ®size);
1382 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1384 ddi_status = ddi_regs_map_setup(nxgep->dip, 2,
1389 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1394 (void) ddi_dev_regsize(nxgep->dip, 3, ®size);
1395 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1397 ddi_status = ddi_regs_map_setup(nxgep->dip, 3,
1402 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1406 nxgep->dev_regs = dev_regs;
1408 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh);
1409 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp);
1411 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh);
1412 NPI_REG_ADD_HANDLE_SET(nxgep,
1415 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh);
1416 NPI_VREG_ADD_HANDLE_SET(nxgep,
1419 NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh);
1420 NPI_V2REG_ADD_HANDLE_SET(nxgep,
1426 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx "
1446 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory"));
1452 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs"));
1457 nxge_unmap_regs(p_nxge_t nxgep)
1459 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs"));
1461 if (isLDOMguest(nxgep)) {
1462 nxge_guest_regs_map_free(nxgep);
1466 if (nxgep->dev_regs) {
1467 if (nxgep->dev_regs->nxge_pciregh) {
1468 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1470 ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh);
1471 nxgep->dev_regs->nxge_pciregh = NULL;
1473 if (nxgep->dev_regs->nxge_regh) {
1474 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1476 ddi_regs_map_free(&nxgep->dev_regs->nxge_regh);
1477 nxgep->dev_regs->nxge_regh = NULL;
1479 if (nxgep->dev_regs->nxge_msix_regh) {
1480 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1482 ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh);
1483 nxgep->dev_regs->nxge_msix_regh = NULL;
1485 if (nxgep->dev_regs->nxge_vir_regh) {
1486 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1488 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh);
1489 nxgep->dev_regs->nxge_vir_regh = NULL;
1491 if (nxgep->dev_regs->nxge_vir2_regh) {
1492 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1494 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh);
1495 nxgep->dev_regs->nxge_vir2_regh = NULL;
1498 kmem_free(nxgep->dev_regs, sizeof (dev_regs_t));
1499 nxgep->dev_regs = NULL;
1502 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs"));
1506 nxge_setup_mutexes(p_nxge_t nxgep)
1513 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes"));
1519 if (isLDOMguest(nxgep)) {
1520 nxgep->interrupt_cookie = 0;
1522 ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0,
1523 &nxgep->interrupt_cookie);
1526 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1533 cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL);
1534 MUTEX_INIT(&nxgep->poll_lock, NULL,
1535 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1540 MUTEX_INIT(nxgep->genlock, NULL,
1541 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1542 MUTEX_INIT(&nxgep->ouraddr_lock, NULL,
1543 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1544 MUTEX_INIT(&nxgep->mif_lock, NULL,
1545 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1546 MUTEX_INIT(&nxgep->group_lock, NULL,
1547 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1548 RW_INIT(&nxgep->filter_lock, NULL,
1549 RW_DRIVER, (void *)nxgep->interrupt_cookie);
1551 classify_ptr = &nxgep->classifier;
1559 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1560 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1562 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1565 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1570 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1580 nxge_destroy_mutexes(p_nxge_t nxgep)
1585 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes"));
1586 RW_DESTROY(&nxgep->filter_lock);
1587 MUTEX_DESTROY(&nxgep->group_lock);
1588 MUTEX_DESTROY(&nxgep->mif_lock);
1589 MUTEX_DESTROY(&nxgep->ouraddr_lock);
1590 MUTEX_DESTROY(nxgep->genlock);
1592 classify_ptr = &nxgep->classifier;
1596 MUTEX_DESTROY(&nxgep->poll_lock);
1597 cv_destroy(&nxgep->poll_cv);
1600 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1607 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes"));
1611 nxge_init(p_nxge_t nxgep)
1615 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init"));
1617 if (nxgep->drv_state & STATE_HW_INITIALIZED) {
1625 status = nxge_alloc_mem_pool(nxgep);
1627 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n"));
1631 if (!isLDOMguest(nxgep)) {
1638 status = nxge_txc_init(nxgep);
1640 NXGE_ERROR_MSG((nxgep,
1649 status = nxge_init_txdma_channels(nxgep);
1651 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n"));
1658 status = nxge_init_rxdma_channels(nxgep);
1660 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n"));
1667 if (isLDOMguest(nxgep)) {
1668 nxgep->drv_state |= STATE_HW_INITIALIZED;
1675 status = nxge_classify_init(nxgep);
1677 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n"));
1684 status = nxge_zcp_init(nxgep);
1686 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n"));
1693 status = nxge_ipp_init(nxgep);
1695 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n"));
1702 status = nxge_mac_init(nxgep);
1704 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n"));
1711 nxge_intrs_enable(nxgep);
1713 nxgep->drv_state |= STATE_HW_INITIALIZED;
1718 nxge_uninit_rxdma_channels(nxgep);
1720 nxge_uninit_txdma_channels(nxgep);
1722 if (!isLDOMguest(nxgep)) {
1723 (void) nxge_txc_uninit(nxgep);
1726 nxge_free_mem_pool(nxgep);
1728 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1733 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x",
1740 nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec)
1742 if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) {
1743 return (timeout(func, (caddr_t)nxgep,
1751 nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid)
1759 nxge_uninit(p_nxge_t nxgep)
1761 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit"));
1763 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
1764 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1766 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1771 if (!isLDOMguest(nxgep)) {
1775 (void) nxge_rx_mac_disable(nxgep);
1780 (void) nxge_ipp_drain(nxgep);
1784 if (nxgep->nxge_timerid) {
1785 nxge_stop_timer(nxgep, nxgep->nxge_timerid);
1786 nxgep->nxge_timerid = 0;
1789 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
1790 (void) nxge_intr_hw_disable(nxgep);
1794 if (!isLDOMguest(nxgep))
1795 (void) nxge_ipp_disable(nxgep);
1798 (void) nxge_classify_uninit(nxgep);
1803 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP);
1804 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP);
1806 nxge_uninit_txdma_channels(nxgep);
1807 nxge_uninit_rxdma_channels(nxgep);
1812 (void) nxge_tx_mac_disable(nxgep);
1814 nxge_free_mem_pool(nxgep);
1825 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
1828 nxgep->drv_state &= ~STATE_HW_INITIALIZED;
1830 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: "
1835 nxge_get64(p_nxge_t nxgep, p_mblk_t mp)
1846 NXGE_REG_RD64(nxgep->npi_handle, reg, ®data);
1852 nxge_put64(p_nxge_t nxgep, p_mblk_t mp)
1860 NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]);
1866 nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...)
1875 if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) {
1877 if (nxgep->nxge_debug_level != nxge_debug_level)
1878 nxgep->nxge_debug_level = nxge_debug_level;
1881 debug_level = (nxgep == NULL) ? nxge_debug_level :
1882 nxgep->nxge_debug_level;
1901 if (nxgep == NULL) {
1905 instance = nxgep->instance;
1961 nxge_test_map_regs(p_nxge_t nxgep)
1971 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs"));
1973 dev_handle = nxgep->dev_regs->nxge_regh;
1974 dev_ptr = (char *)nxgep->dev_regs->nxge_regp;
1976 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1977 cfg_handle = nxgep->dev_regs->nxge_pciregh;
1978 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp;
1980 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1982 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1985 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1989 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1996 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2003 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2007 cfg_handle = nxgep->dev_regs->nxge_pciregh;
2008 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp;
2009 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2026 nxge_suspend(p_nxge_t nxgep)
2028 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend"));
2030 nxge_intrs_disable(nxgep);
2031 nxge_destroy_dev(nxgep);
2033 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend"));
2037 nxge_resume(p_nxge_t nxgep)
2041 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume"));
2043 nxgep->suspended = DDI_RESUME;
2044 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
2045 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START);
2046 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START);
2047 (void) nxge_rx_mac_enable(nxgep);
2048 (void) nxge_tx_mac_enable(nxgep);
2049 nxge_intrs_enable(nxgep);
2050 nxgep->suspended = 0;
2052 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2058 nxge_setup_dev(p_nxge_t nxgep)
2062 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d",
2063 nxgep->mac.portnum));
2065 status = nxge_link_init(nxgep);
2067 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) {
2068 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2069 "port%d Bad register acc handle", nxgep->mac.portnum));
2074 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2081 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2083 nxgep->mac.portnum, status));
2089 nxge_destroy_dev(p_nxge_t nxgep)
2091 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev"));
2093 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
2095 (void) nxge_hw_stop(nxgep);
2097 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev"));
2101 nxge_setup_system_dma_pages(p_nxge_t nxgep)
2109 NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages"));
2110 nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1);
2111 if (nxgep->niu_type != N2_NIU) {
2112 iommu_pagesize = dvma_pagesize(nxgep->dip);
2113 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2116 nxgep->sys_page_sz,
2117 ddi_ptob(nxgep->dip, (ulong_t)1),
2118 nxgep->rx_default_block_size,
2122 if (nxgep->sys_page_sz == iommu_pagesize) {
2124 nxgep->sys_page_sz = 0x4000;
2126 if (nxgep->sys_page_sz > iommu_pagesize)
2127 nxgep->sys_page_sz = iommu_pagesize;
2131 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1);
2132 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2135 nxgep->sys_page_sz,
2136 ddi_ptob(nxgep->dip, (ulong_t)1),
2137 nxgep->rx_default_block_size,
2138 nxgep->sys_page_mask));
2141 switch (nxgep->sys_page_sz) {
2143 nxgep->sys_page_sz = 0x1000;
2144 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1);
2145 nxgep->rx_default_block_size = 0x1000;
2146 nxgep->rx_bksize_code = RBR_BKSIZE_4K;
2149 nxgep->rx_default_block_size = 0x1000;
2150 nxgep->rx_bksize_code = RBR_BKSIZE_4K;
2153 nxgep->rx_default_block_size = 0x2000;
2154 nxgep->rx_bksize_code = RBR_BKSIZE_8K;
2157 nxgep->rx_default_block_size = 0x4000;
2158 nxgep->rx_bksize_code = RBR_BKSIZE_16K;
2161 nxgep->rx_default_block_size = 0x8000;
2162 nxgep->rx_bksize_code = RBR_BKSIZE_32K;
2167 nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz;
2169 nxgep->rx_default_block_size = 0x2000;
2170 nxgep->rx_bksize_code = RBR_BKSIZE_8K;
2175 ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr,
2177 &nxgep->dmasparehandle);
2179 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2185 ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL,
2186 (caddr_t)nxgep->dmasparehandle,
2187 sizeof (nxgep->dmasparehandle),
2192 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2199 nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle);
2200 (void) ddi_dma_unbind_handle(nxgep->dmasparehandle);
2203 ddi_dma_free_handle(&nxgep->dmasparehandle);
2210 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2216 nxge_alloc_mem_pool(p_nxge_t nxgep)
2220 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool"));
2222 status = nxge_alloc_rx_mem_pool(nxgep);
2227 status = nxge_alloc_tx_mem_pool(nxgep);
2229 nxge_free_rx_mem_pool(nxgep);
2233 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool"));
2238 nxge_free_mem_pool(p_nxge_t nxgep)
2240 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool"));
2242 nxge_free_rx_mem_pool(nxgep);
2243 nxge_free_tx_mem_pool(nxgep);
2245 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool"));
2249 nxge_alloc_rx_mem_pool(p_nxge_t nxgep)
2266 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool"));
2268 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2312 NXGE_DEBUG_MSG((nxgep, MEM_CTL,
2319 NXGE_DEBUG_MSG((nxgep, MEM_CTL,
2333 if (nxgep->niu_type == N2_NIU) {
2355 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: "
2364 if (nxgep->niu_type == N2_NIU) {
2365 uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size *
2369 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2377 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2389 nxgep->nxge_port_rbr_size = nxge_port_rbr_size;
2390 nxgep->nxge_port_rcr_size = nxge_port_rcr_size;
2391 nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size;
2392 nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size;
2397 nxgep->rx_buf_pool_p = dma_poolp;
2402 nxgep->rx_cntl_pool_p = dma_cntl_poolp;
2406 nxgep->rx_rbr_rings =
2408 nxgep->rx_rbr_rings->rbr_rings =
2410 nxgep->rx_rcr_rings =
2412 nxgep->rx_rcr_rings->rcr_rings =
2414 nxgep->rx_mbox_areas_p =
2416 nxgep->rx_mbox_areas_p->rxmbox_areas =
2419 nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas =
2422 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2435 * nxgep
2455 p_nxge_t nxgep,
2465 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb"));
2476 rx_buf_alloc_size = (nxgep->rx_default_block_size *
2477 (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size));
2479 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
2480 num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel];
2483 nxgep, channel, data, rx_buf_alloc_size,
2484 nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) {
2488 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): "
2494 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
2497 nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size))
2499 nxge_free_rx_cntl_dma(nxgep, *control);
2501 nxge_free_rx_buf_dma(nxgep, *data, *num_chunks);
2505 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2513 p_nxge_t nxgep,
2520 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb"));
2522 data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
2523 num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel];
2524 nxge_free_rx_buf_dma(nxgep, data, num_chunks);
2526 nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0;
2527 nxgep->rx_buf_pool_p->num_chunks[channel] = 0;
2529 control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
2530 nxge_free_rx_cntl_dma(nxgep, control);
2532 nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0;
2537 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb"));
2541 nxge_free_rx_mem_pool(p_nxge_t nxgep)
2545 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool"));
2547 if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) {
2548 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2553 if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) {
2554 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2560 KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p,
2562 KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t));
2564 KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks,
2566 KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p,
2568 KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t));
2570 nxgep->rx_buf_pool_p = 0;
2571 nxgep->rx_cntl_pool_p = 0;
2573 KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings,
2575 KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t));
2576 KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings,
2578 KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t));
2579 KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas,
2581 KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t));
2583 nxgep->rx_rbr_rings = 0;
2584 nxgep->rx_rcr_rings = 0;
2585 nxgep->rx_mbox_areas_p = 0;
2587 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool"));
2592 nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel,
2603 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma"));
2609 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2630 if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) {
2635 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2658 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) {
2663 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2670 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2676 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma,
2683 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2692 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2702 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2714 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2723 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2729 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2741 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2749 nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap,
2754 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2761 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2767 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma"));
2772 nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel,
2778 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma"));
2786 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma,
2803 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2811 nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap)
2813 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma"));
2820 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma"));
2832 nxge_t *nxgep,
2844 if (nxgep->niu_type == N2_NIU) {
2855 if (nxgep->niu_type == N2_NIU) {
2857 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2864 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2887 * nxgep
2907 p_nxge_t nxgep,
2917 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb"));
2919 if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK)
2927 dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel];
2928 num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel];
2930 dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel];
2939 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2944 status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p,
2954 status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p,
2957 nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks);
2967 p_nxge_t nxgep,
2974 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb"));
2976 data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel];
2977 num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel];
2978 nxge_free_tx_buf_dma(nxgep, data, num_chunks);
2980 nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0;
2981 nxgep->tx_buf_pool_p->num_chunks[channel] = 0;
2983 control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel];
2984 nxge_free_tx_cntl_dma(nxgep, control);
2986 nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0;
2991 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb"));
3001 * nxgep
3009 nxge_alloc_tx_mem_pool(p_nxge_t nxgep)
3019 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool"));
3021 p_cfgp = &nxgep->pt_config.hw_config;
3038 NXGE_DEBUG_MSG((nxgep, MEM_CTL,
3053 if (nxgep->niu_type == N2_NIU) {
3061 nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size;
3069 nxgep->tx_buf_pool_p = dma_poolp;
3075 nxgep->tx_cntl_pool_p = dma_cntl_poolp;
3079 nxgep->tx_rings =
3081 nxgep->tx_rings->rings =
3083 nxgep->tx_mbox_areas_p =
3085 nxgep->tx_mbox_areas_p->txmbox_areas_p =
3088 nxgep->tx_rings->ndmas = p_cfgp->tdc.owned;
3090 NXGE_DEBUG_MSG((nxgep, MEM_CTL,
3098 nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel,
3108 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma"));
3142 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) {
3146 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma,
3161 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3170 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3178 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3187 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3195 nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap,
3200 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma"));
3209 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma"));
3214 nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel,
3220 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma"));
3227 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma,
3244 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3252 nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap)
3254 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma"));
3261 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma"));
3272 * nxgep
3280 nxge_free_tx_mem_pool(p_nxge_t nxgep)
3284 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool"));
3286 if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) {
3287 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3292 if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) {
3293 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3300 KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p,
3302 KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t));
3304 nxgep->tx_mbox_areas_p = 0;
3307 KMEM_FREE(nxgep->tx_rings->rings,
3309 KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t));
3311 nxgep->tx_rings = 0;
3314 KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p,
3316 KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t));
3318 nxgep->tx_cntl_pool_p = 0;
3321 KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks,
3323 KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p,
3325 KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t));
3327 nxgep->tx_buf_pool_p = 0;
3329 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool"));
3334 nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method,
3346 if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) {
3351 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3361 ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp,
3364 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3382 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3390 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3406 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3421 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3441 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3453 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3468 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3484 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
3498 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3509 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3514 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3537 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3562 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3595 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: "
3762 p_nxge_t nxgep = (p_nxge_t)arg;
3764 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start"));
3769 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) {
3773 if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) {
3774 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
3780 if (!isLDOMguest(nxgep)) {
3781 (void) nxge_rx_mac_disable(nxgep);
3787 MUTEX_ENTER(nxgep->genlock);
3792 if (nxge_init(nxgep) != NXGE_OK) {
3793 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3795 MUTEX_EXIT(nxgep->genlock);
3802 if (!isLDOMguest(nxgep))
3803 nxgep->nxge_timerid = nxge_start_timer(nxgep,
3807 nxge_hio_start_timer(nxgep);
3810 nxgep->link_notify = B_TRUE;
3811 nxgep->link_check_count = 0;
3812 nxgep->nxge_mac_state = NXGE_MAC_STARTED;
3817 MUTEX_EXIT(nxgep->genlock);
3823 if (!isLDOMguest(nxgep)) {
3824 if (nxge_rx_mac_enable(nxgep) != NXGE_OK) {
3825 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3833 nxge_intr_hw_enable(nxgep);
3841 if (nxge_hio_rdc_enable(nxgep) != NXGE_OK) {
3842 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3847 if (nxge_hio_rdc_intr_arm(nxgep, B_TRUE) != NXGE_OK) {
3848 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3854 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start"));
3859 nxge_check_groups_stopped(p_nxge_t nxgep)
3864 if (nxgep->rx_hio_groups[i].started)
3877 p_nxge_t nxgep = (p_nxge_t)arg;
3880 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop"));
3885 groups_stopped = nxge_check_groups_stopped(nxgep);
3889 nxgep->instance);
3893 if (!isLDOMguest(nxgep)) {
3897 (void) nxge_rx_mac_disable(nxgep);
3902 (void) nxge_ipp_drain(nxgep);
3907 nxge_intr_hw_disable(nxgep);
3911 (void) nxge_hio_rdc_intr_arm(nxgep, B_FALSE);
3918 MUTEX_ENTER(nxgep->genlock);
3920 nxgep->nxge_mac_state = NXGE_MAC_STOPPING;
3921 if (nxgep->nxge_timerid) {
3922 nxge_stop_timer(nxgep, nxgep->nxge_timerid);
3923 nxgep->nxge_timerid = 0;
3929 nxge_uninit(nxgep);
3931 nxgep->nxge_mac_state = NXGE_MAC_STOPPED;
3936 MUTEX_EXIT(nxgep->genlock);
3937 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop"));
3943 p_nxge_t nxgep = (p_nxge_t)arg;
3946 NXGE_DEBUG_MSG((nxgep, MAC_CTL,
3951 if (nxge_add_mcast_addr(nxgep, &addrp)) {
3952 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3957 if (nxge_del_mcast_addr(nxgep, &addrp)) {
3958 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3964 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst"));
3972 p_nxge_t nxgep = (p_nxge_t)arg;
3974 NXGE_DEBUG_MSG((nxgep, MAC_CTL,
3977 if (nxge_set_promisc(nxgep, on)) {
3978 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3983 NXGE_DEBUG_MSG((nxgep, MAC_CTL,
3992 p_nxge_t nxgep = (p_nxge_t)arg;
3998 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl"));
4004 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd));
4008 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid"));
4045 nxge_err_inject(nxgep, wq, mp);
4053 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4065 nxge_loopback_ioctl(nxgep, wq, mp, iocp);
4084 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4086 nxge_hw_ioctl(nxgep, wq, mp, iocp);
4089 if (nxge_rxclass_ioctl(nxgep, wq, mp->b_cont) < 0)
4096 if (nxge_rxhash_ioctl(nxgep, wq, mp->b_cont) < 0)
4103 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl"));
4109 nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, boolean_t factory)
4115 mmac_info = &nxgep->nxge_mmac_info;
4117 mmac_stats = &nxgep->statsp->mmac_stats;
4138 nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, int slot,
4152 portn = nxgep->mac.portnum;
4155 if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET,
4156 nxgep->function_num, addrn, &altmac) != NPI_SUCCESS)
4163 clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
4172 if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET,
4173 nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) {
4189 if (npi_mac_altaddr_enable(nxgep->npi_handle,
4190 nxgep->function_num, addrn) != NPI_SUCCESS) {
4206 p_nxge_t nxgep = arg;
4212 mutex_enter(nxgep->genlock);
4218 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
4219 status = nxge_init(nxgep);
4221 mutex_exit(nxgep->genlock);
4226 mmac_info = &nxgep->nxge_mmac_info;
4228 mutex_exit(nxgep->genlock);
4251 if ((err = nxge_altmac_set(nxgep, (uint8_t *)maddr, slot, rdctbl,
4253 mutex_exit(nxgep->genlock);
4261 nxge_mmac_kstat_update(nxgep, slot, B_FALSE);
4263 mutex_exit(nxgep->genlock);
4274 p_nxge_t nxgep = arg;
4281 mutex_enter(nxgep->genlock);
4287 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
4288 status = nxge_init(nxgep);
4290 mutex_exit(nxgep->genlock);
4295 mmac_info = &nxgep->nxge_mmac_info;
4297 mutex_exit(nxgep->genlock);
4301 portn = nxgep->mac.portnum;
4308 if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn)
4330 nxge_mmac_kstat_update(nxgep, slot, B_FALSE);
4338 mutex_exit(nxgep->genlock);
4351 nxge_t *nxgep = arg;
4355 mutex_enter(nxgep->genlock);
4357 mmac_info = &nxgep->nxge_mmac_info;
4365 mutex_exit(nxgep->genlock);
4372 nxge_t *nxgep = arg;
4377 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4387 if (!isLDOMguest(nxgep)) {
4388 mutex_enter(nxgep->genlock);
4390 nxgep->nxge_mmac_info.num_factory_mmac;
4392 mutex_exit(nxgep->genlock);
4400 if (nxgep->soft_lso_enable) {
4417 p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config;
4419 mutex_enter(nxgep->genlock);
4421 if (isLDOMguest(nxgep)) {
4445 NXGE_DEBUG_MSG((nxgep, RX_CTL,
4452 if (isLDOMguest(nxgep)) {
4477 NXGE_MAX_TDC_GROUPS / nxgep->nports - 1;
4483 NXGE_DEBUG_MSG((nxgep, TX_CTL,
4487 mutex_exit(nxgep->genlock);
4499 mutex_enter(nxgep->genlock);
4500 if (isLDOMservice(nxgep)) {
4502 mshares->ms_handle = (void *)nxgep;
4510 mutex_exit(nxgep->genlock);
4512 mutex_exit(nxgep->genlock);
4558 nxge_t *nxgep = barg;
4559 p_nxge_param_t param_arr = nxgep->param_arr;
4560 p_nxge_stats_t statsp = nxgep->statsp;
4563 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop"));
4565 mutex_enter(nxgep->genlock);
4572 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4574 mutex_exit(nxgep->genlock);
4580 nxgep->param_en_1000fdx =
4585 nxgep->param_en_100fdx =
4590 nxgep->param_en_10fdx =
4601 cur_mtu = nxgep->mac.default_mtu;
4605 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4607 new_mtu, nxgep->mac.is_jumbo));
4614 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) {
4625 old_framesize = (uint32_t)nxgep->mac.maxframesize;
4626 nxgep->mac.maxframesize = (uint16_t)
4628 if (nxge_mac_set_framesize(nxgep)) {
4629 nxgep->mac.maxframesize =
4635 nxgep->mac.default_mtu = new_mtu;
4636 nxgep->mac.is_jumbo = (new_mtu > NXGE_DEFAULT_MTU);
4638 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4640 new_mtu, nxgep->mac.maxframesize));
4668 if ((err == 0) && !isLDOMguest(nxgep)) {
4669 if (!nxge_param_link_update(nxgep)) {
4679 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4681 err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, pr_val);
4689 mutex_exit(nxgep->genlock);
4691 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4700 nxge_t *nxgep = barg;
4701 p_nxge_param_t param_arr = nxgep->param_arr;
4702 p_nxge_stats_t statsp = nxgep->statsp;
4704 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4747 *(uint8_t *)pr_val = nxgep->param_en_1000fdx;
4755 *(uint8_t *)pr_val = nxgep->param_en_100fdx;
4763 *(uint8_t *)pr_val = nxgep->param_en_10fdx;
4767 return (nxge_get_priv_prop(nxgep, pr_name, pr_valsize,
4781 nxge_t *nxgep = barg;
4782 p_nxge_stats_t statsp = nxgep->statsp;
4834 mutex_enter(nxgep->genlock);
4843 mutex_exit(nxgep->genlock);
4894 nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize,
4897 p_nxge_param_t param_arr = nxgep->param_arr;
4901 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4906 err = nxge_param_rx_intr_time(nxgep, NULL, NULL,
4910 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4916 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4921 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4929 err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL,
4933 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4939 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4944 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4959 err = nxge_param_set_ip_opt(nxgep, NULL,
4963 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4977 err = nxge_param_set_ip_opt(nxgep, NULL,
4981 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
4994 err = nxge_param_set_ip_opt(nxgep, NULL,
4998 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5011 err = nxge_param_set_ip_opt(nxgep, NULL,
5015 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5029 err = nxge_param_set_ip_opt(nxgep, NULL,
5033 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5047 err = nxge_param_set_ip_opt(nxgep, NULL,
5051 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5064 err = nxge_param_set_ip_opt(nxgep, NULL,
5068 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5081 err = nxge_param_set_ip_opt(nxgep, NULL,
5085 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5094 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5101 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5104 pr_name, nxgep->soft_lso_enable, pr_val, result));
5109 if (nxgep->soft_lso_enable == (uint32_t)result) {
5110 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5112 nxgep->soft_lso_enable, result));
5117 nxgep->soft_lso_enable = (int)result;
5119 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5130 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val,
5135 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val,
5144 nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize,
5147 p_nxge_param_t param_arr = nxgep->param_arr;
5152 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5158 nxgep->function_num);
5159 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5162 pr_name, nxgep->function_num, valstr));
5171 nxgep->vpd_info.ver);
5172 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5175 pr_name, nxgep->vpd_info.ver, valstr));
5183 switch (nxgep->mac.portmode) {
5186 nxgep->hot_swappable_phy ?
5191 nxgep->hot_swappable_phy ?
5197 nxgep->hot_swappable_phy ?
5202 nxgep->hot_swappable_phy ?
5207 "10G serdes %s", nxgep->hot_swappable_phy ?
5212 nxgep->hot_swappable_phy ?
5217 "1G TN1010 copper %s", nxgep->hot_swappable_phy ?
5222 "10G TN1010 copper %s", nxgep->hot_swappable_phy ?
5227 "1G rgmii fiber %s", nxgep->hot_swappable_phy ?
5236 nxgep->hot_swappable_phy ?
5241 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5252 nxgep->hot_swappable_phy ?
5255 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5258 pr_name, nxgep->hot_swappable_phy, valstr));
5269 nxgep->intr_timeout);
5270 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5273 (uint32_t)nxgep->intr_timeout));
5280 nxgep->intr_threshold);
5281 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5283 pr_name, (uint32_t)nxgep->intr_threshold));
5290 err = nxge_dld_get_ip_opt(nxgep,
5296 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5302 err = nxge_dld_get_ip_opt(nxgep,
5308 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5313 err = nxge_dld_get_ip_opt(nxgep,
5319 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5325 err = nxge_dld_get_ip_opt(nxgep,
5331 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5337 err = nxge_dld_get_ip_opt(nxgep,
5343 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5349 err = nxge_dld_get_ip_opt(nxgep,
5355 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5361 err = nxge_dld_get_ip_opt(nxgep,
5367 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5373 err = nxge_dld_get_ip_opt(nxgep,
5379 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5387 "%d", nxgep->soft_lso_enable);
5389 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5391 pr_name, nxgep->soft_lso_enable));
5397 if (nxgep->param_arr[param_anar_10gfdx].value != 0) {
5407 if (nxgep->param_arr[param_anar_pause].value != 0) {
5426 NXGE_DEBUG_MSG((nxgep, NXGE_CTL,
5540 p_nxge_t nxgep = rhp->nxgep;
5544 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index;
5545 ring = nxgep->tx_rings->rings[channel];
5559 p_nxge_t nxgep = rhp->nxgep;
5563 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index;
5564 ring = nxgep->tx_rings->rings[channel];
5576 p_nxge_t nxgep = rhp->nxgep;
5581 channel = nxgep->pt_config.hw_config.start_rdc + rhp->index;
5582 ring = nxgep->rx_rcr_rings->rcr_rings[channel];
5593 for (i = 0; i < nxgep->ldgvp->maxldvs; i++) {
5594 if ((nxgep->ldgvp->ldvp[i].is_rxdma) &&
5595 (nxgep->ldgvp->ldvp[i].channel == channel)) {
5596 ring->ldvp = &nxgep->ldgvp->ldvp[i];
5597 ring->ldgp = nxgep->ldgvp->ldvp[i].ldgp;
5614 p_nxge_t nxgep = rhp->nxgep;
5618 channel = nxgep->pt_config.hw_config.start_rdc + rhp->index;
5619 ring = nxgep->rx_rcr_rings->rcr_rings[channel];
5631 nxge_ring_get_htable_idx(p_nxge_t nxgep, mac_ring_type_t type, uint32_t channel)
5636 if (isLDOMguest(nxgep)) {
5637 return (nxge_hio_get_dc_htable_idx(nxgep,
5643 ASSERT(nxgep->ldgvp != NULL);
5647 for (i = 0; i < nxgep->ldgvp->maxldvs; i++) {
5648 if ((nxgep->ldgvp->ldvp[i].is_txdma) &&
5649 (nxgep->ldgvp->ldvp[i].channel == channel)) {
5651 nxgep->ldgvp->ldvp[i].ldgp->htable_idx);
5657 for (i = 0; i < nxgep->ldgvp->maxldvs; i++) {
5658 if ((nxgep->ldgvp->ldvp[i].is_rxdma) &&
5659 (nxgep->ldgvp->ldvp[i].channel == channel)) {
5661 nxgep->ldgvp->ldvp[i].ldgp->htable_idx);
5676 p_nxge_t nxgep = (p_nxge_t)arg;
5677 p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config;
5683 ASSERT(nxgep != NULL);
5687 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
5695 NXGE_DEBUG_MSG((nxgep, TX_CTL,
5700 rhandlep = &nxgep->tx_ring_handles[index];
5701 rhandlep->nxgep = nxgep;
5705 channel = nxgep->pt_config.hw_config.tdc.start + index;
5707 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
5708 htable_idx = nxge_ring_get_htable_idx(nxgep, rtype,
5729 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
5731 NXGE_DEBUG_MSG((nxgep, RX_CTL,
5739 nxge_rindex = nxge_get_rxring_index(nxgep, rg_index, index);
5740 channel = nxgep->pt_config.hw_config.start_rdc + index;
5741 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
5744 rhandlep = &nxgep->rx_ring_handles[nxge_rindex];
5745 rhandlep->nxgep = nxgep;
5759 htable_idx = nxge_ring_get_htable_idx(nxgep, rtype,
5780 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_fill_ring 0x%x", rtype));
5796 nxge = rgroup->nxgep;
5866 nxge = rgroup->nxgep;
5903 nxge_add_intrs(p_nxge_t nxgep)
5911 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs"));
5913 nxgep->nxge_intr_type.intr_registered = B_FALSE;
5914 nxgep->nxge_intr_type.intr_enabled = B_FALSE;
5915 nxgep->nxge_intr_type.msi_intx_cnt = 0;
5916 nxgep->nxge_intr_type.intr_added = 0;
5917 nxgep->nxge_intr_type.niu_msi_enable = B_FALSE;
5918 nxgep->nxge_intr_type.intr_type = 0;
5920 if (nxgep->niu_type == N2_NIU) {
5921 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE;
5923 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE;
5927 if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types))
5929 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: "
5934 nxgep->nxge_intr_type.intr_types = intr_types;
5936 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: "
5947 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: "
5953 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: "
5957 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: "
5962 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: "
5967 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: "
5976 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: "
5981 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: "
5986 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: "
5992 nxgep->nxge_intr_type.intr_type = type;
5995 nxgep->nxge_intr_type.niu_msi_enable) {
5996 if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) {
5997 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6003 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: "
6005 nxgep->nxge_intr_type.intr_registered = B_TRUE;
6007 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
6015 if (!nxgep->nxge_intr_type.intr_registered) {
6016 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: "
6021 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs"));
6026 nxge_add_intrs_adv(p_nxge_t nxgep)
6031 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv"));
6033 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
6035 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x",
6041 return (nxge_add_intrs_adv_type(nxgep, intr_type));
6044 return (nxge_add_intrs_adv_type_fix(nxgep, intr_type));
6054 nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type)
6056 dev_info_t *dip = nxgep->dip;
6069 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type"));
6070 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
6075 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6083 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6089 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6095 nrequest = nxge_create_msi_property(nxgep);
6098 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6118 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6130 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6139 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6152 switch (nxgep->niu_type) {
6154 status = nxge_ldgv_init(nxgep, &nactual, &nrequired);
6158 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired);
6163 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6175 ldgp = nxgep->ldgvp->ldgp;
6180 arg2 = nxgep;
6183 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6191 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6200 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6207 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6220 (void) nxge_ldgv_uninit(nxgep);
6231 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
6239 (void) nxge_intr_ldgv_init(nxgep);
6241 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type"));
6248 nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type)
6250 dev_info_t *dip = nxgep->dip;
6263 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix"));
6264 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
6269 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6277 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6283 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6294 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6303 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6316 switch (nxgep->niu_type) {
6318 status = nxge_ldgv_init(nxgep, &nactual, &nrequired);
6322 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired);
6327 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6339 ldgp = nxgep->ldgvp->ldgp;
6342 if (nxgep->niu_type != N2_NIU) {
6347 arg2 = nxgep;
6350 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6358 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6369 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
6382 (void) nxge_ldgv_uninit(nxgep);
6395 status = nxge_intr_ldgv_init(nxgep);
6396 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix"));
6402 nxge_remove_intrs(p_nxge_t nxgep)
6407 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs"));
6408 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
6410 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6415 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced"));
6434 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
6451 (void) nxge_ldgv_uninit(nxgep);
6453 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip,
6456 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs"));
6461 nxge_intrs_enable(p_nxge_t nxgep)
6467 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable"));
6469 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
6472 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: "
6478 NXGE_DEBUG_MSG((nxgep, INT_CTL,
6486 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable "
6492 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable "
6502 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable"));
6507 nxge_intrs_disable(p_nxge_t nxgep)
6512 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable"));
6514 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type;
6517 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: "
6532 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable"));
6536 nxge_mac_register(p_nxge_t nxgep)
6541 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register"));
6547 macp->m_driver = nxgep;
6548 macp->m_dip = nxgep->dip;
6549 if (!isLDOMguest(nxgep)) {
6550 macp->m_src_addr = nxgep->ouraddr.ether_addr_octet;
6558 nxgep->mac.default_mtu = nxgep->mac.maxframesize -
6560 macp->m_max_sdu = nxgep->mac.default_mtu;
6563 if (isLDOMguest(nxgep))
6568 NXGE_DEBUG_MSG((nxgep, MAC_CTL,
6571 nxgep->instance,
6573 nxgep->mac.maxframesize,
6576 status = mac_register(macp, &nxgep->mach);
6577 if (isLDOMguest(nxgep)) {
6586 status, nxgep->instance);
6590 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success "
6591 "(instance %d)", nxgep->instance));
6597 nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp)
6606 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject"));
6627 nxge_ipp_inject_err(nxgep, err_id);
6630 nxge_txc_inject_err(nxgep, err_id);
6633 nxge_txdma_inject_err(nxgep, err_id, chan);
6636 nxge_rxdma_inject_err(nxgep, err_id, chan);
6639 nxge_zcp_inject_err(nxgep, err_id);
6656 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject"));
6662 nxge_init_common_dev(p_nxge_t nxgep)
6667 ASSERT(nxgep != NULL);
6669 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device"));
6671 p_dip = nxgep->p_dip;
6673 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6675 nxgep->function_num));
6680 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6683 nxgep->function_num,
6687 nxgep->nxge_hw_p = hw_p;
6689 hw_p->nxge_p[nxgep->function_num] = nxgep;
6690 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6694 nxgep->function_num,
6708 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6711 nxgep->function_num,
6716 nxgep->nxge_hw_p = hw_p;
6718 hw_p->nxge_p[nxgep->function_num] = nxgep;
6720 if (nxgep->niu_type == N2_NIU) {
6740 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0,
6746 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6751 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6760 (void) nxge_scan_ports_phy(nxgep, nxge_hw_list);
6765 nxgep->platform_type = hw_p->platform_type;
6766 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxgep->platform_type %d",
6767 nxgep->platform_type));
6768 if (nxgep->niu_type != N2_NIU) {
6769 nxgep->niu_type = hw_p->niu_type;
6772 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6775 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device"));
6781 nxge_uninit_common_dev(p_nxge_t nxgep)
6788 ASSERT(nxgep != NULL);
6790 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device"));
6791 if (nxgep->nxge_hw_p == NULL) {
6792 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6801 if (nxgep->nxge_hw_p == hw_p &&
6802 p_dip == nxgep->p_dip &&
6803 nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC &&
6806 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6810 nxgep->function_num,
6821 if (!isLDOMguest(nxgep)) {
6823 (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
6826 (void) nxge_fzc_rdc_tbl_unbind(nxgep,
6830 nxge_grp_cleanup(nxgep);
6836 hw_p->nxge_p[nxgep->function_num] = NULL;
6845 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6850 nxgep->function_num,
6855 nxge_hio_uninit(nxgep);
6858 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6863 nxgep->function_num,
6869 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6874 nxgep->function_num,
6881 nxgep->nxge_hw_p = NULL;
6891 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6895 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device"));
6904 nxge_get_nports(p_nxge_t nxgep)
6908 switch (nxgep->niu_type) {
6921 switch (nxgep->platform_type) {
6947 nxge_create_msi_property(p_nxge_t nxgep)
6952 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property"));
6954 switch (nxgep->mac.portmode) {
6958 (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip,
6965 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6971 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6984 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6988 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
6990 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip,
6995 (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip,
6997 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
7003 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
7008 NXGE_DEBUG_MSG((nxgep, MOD_CTL,
7010 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip,
7015 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property"));
7037 nxge_niu_peu_reset(p_nxge_t nxgep)
7044 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset"));
7045 if ((hw_p = nxgep->nxge_hw_p) == NULL) {
7046 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
7051 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
7053 hw_p->flags, nxgep->nxge_link_poll_timerid,
7054 nxgep->nxge_timerid));
7063 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
7065 "nxgep $%p", i, fnxgep));
7068 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
7076 if (fnxgep && fnxgep != nxgep &&
7078 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
7083 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
7095 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
7105 rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh,
7107 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
7115 pci_config_put32(nxgep->dev_regs->nxge_pciregh,
7117 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
7125 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset"));
7129 nxge_set_pci_replay_timeout(p_nxge_t nxgep)
7134 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout"));
7137 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
7143 dev_regs = nxgep->dev_regs;
7144 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
7149 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
7159 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
7169 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
7174 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout"));
7191 p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
7193 if (nxgep == NULL)
7198 nxgep->nxge_debug_level = NO_DEBUG;
7204 if (nxgep->mac.linkchkmode == LINKCHK_INTR) {
7205 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
7208 (void) nxge_intr_hw_disable(nxgep);
7213 (void) nxge_rx_mac_disable(nxgep);
7216 if (!isLDOMguest(nxgep))
7217 (void) nxge_ipp_disable(nxgep);
7222 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP);
7223 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP);
7228 (void) nxge_tx_mac_disable(nxgep);