Lines Matching defs:nxge_port_rbr_size
2261 uint32_t nxge_port_rbr_size;
2293 nxge_port_rbr_size = p_all_cfgp->rbr_size;
2296 if (!nxge_port_rbr_size) {
2297 nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT;
2299 if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) {
2300 nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH *
2301 (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1));
2304 p_all_cfgp->rbr_size = nxge_port_rbr_size;
2311 if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) {
2315 nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS));
2316 nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS;
2335 if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) ||
2336 (!ISP2(nxge_port_rbr_size))) {
2337 nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX;
2350 rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size;
2356 "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d "
2359 nxge_port_rbr_size, nxge_port_rbr_spare_size,
2366 (nxge_port_rbr_size + nxge_port_rbr_spare_size));
2389 nxgep->nxge_port_rbr_size = nxge_port_rbr_size;
2477 (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size));