Lines Matching refs:ESR_REG_WR
2079 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0);
2081 ESR_REG_WR(handle, ESR_RESET_REG, 0x0);
2085 ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG,
2088 ESR_REG_WR(handle, ESR_0_CONTROL_REG,
2103 ESR_REG_WR(handle,
2110 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0);
2115 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_1);
2117 ESR_REG_WR(handle, ESR_RESET_REG, 0x0);
2121 ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG,
2124 ESR_REG_WR(handle, ESR_1_CONTROL_REG,
2139 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG,
2143 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0);
2335 ESR_REG_WR(handle, ESR_RESET_REG, val);
2338 ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG,
2342 ESR_REG_WR(handle, ESR_0_CONTROL_REG, ESR_CTL_1G_SERDES);
2347 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG,
2350 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0);
2356 ESR_REG_WR(handle, ESR_RESET_REG, val);
2363 ESR_REG_WR(handle, ESR_RESET_REG, val);
2366 ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG,
2370 ESR_REG_WR(handle, ESR_1_CONTROL_REG, ESR_CTL_1G_SERDES);
2375 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG,
2378 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0);
2384 ESR_REG_WR(handle, ESR_RESET_REG, val);
6617 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0 | ESR_RESET_1);
6619 ESR_REG_WR(handle, ESR_CONFIG_REG, 0);