Lines Matching defs:tx_cfg_h
1475 esr_ti_cfgtx_h_t tx_cfg_h;
1493 tx_cfg_h.value = 0;
1646 ESR_N2_TX_CFG_H_REG_ADDR(chan), tx_cfg_h.value)) != NXGE_OK)
1653 "==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_h 0x%x",
1654 portn, chan, tx_cfg_h.value));
1700 k_esr_ti_cfgtx_h_t tx_cfg_h;
1717 tx_cfg_h.value = 0;
1762 tx_cfg_h.value = nxgep->srds_prop.tx_cfg_h;
1766 tx_cfg_h.bits.msync = K_CFGTX_ENABLE_MSYNC;
1769 "==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
1770 portn, tx_cfg_h.value));
1817 tx_cfg_h.bits.loopback = K_CFGTX_INNER_CML_ENA_LOOPBACK;
1823 "loopback 0x%x", portn, tx_cfg_h.value));
1854 tx_cfg_h.bits.msync = K_CFGTX_ENABLE_MSYNC;
1856 "==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
1857 portn, tx_cfg_h.value));
1874 "==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
1907 tx_cfg_h.bits.loopback = TESTCFG_INNER_CML_DIS_LOOPBACK;
1915 tx_cfg_h.value)) != NXGE_OK) {
1944 ESR_N2_TX_CFG_H_REG_ADDR(chan), tx_cfg_h.value)) != NXGE_OK)
1953 "chan %d tx_cfg_h 0x%x", portn, chan, tx_cfg_h.value));