Lines Matching defs:rx_cfg_h
1473 esr_ti_cfgrx_h_t rx_cfg_h;
1495 rx_cfg_h.value = 0;
1533 rx_cfg_h.bits.eq = CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF;
1588 rx_cfg_h.bits.eq = CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF;
1664 ESR_N2_RX_CFG_H_REG_ADDR(chan), rx_cfg_h.value)) != NXGE_OK)
1672 "==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_h 0x%x",
1673 portn, chan, rx_cfg_h.value));
1698 k_esr_ti_cfgrx_h_t rx_cfg_h;
1719 rx_cfg_h.value = 0;
1786 rx_cfg_h.value = nxgep->srds_prop.rx_cfg_h;
1789 rx_cfg_h.bits.eq = K_CFGRX_EQ_ADAPTIVE;
1793 "==> nxge_n2_kt_serdes_init port<%d> rx_cfg_h 0x%x",
1794 portn, rx_cfg_h.value));
1818 rx_cfg_h.bits.loopback = K_CFGTX_INNER_CML_ENA_LOOPBACK;
1871 rx_cfg_h.bits.eq = K_CFGRX_EQ_ADAPTIVE_LF_365MHZ_ZF;
1875 portn, rx_cfg_h.value));
1965 ESR_N2_RX_CFG_H_REG_ADDR(chan), rx_cfg_h.value))
1975 "chan %d rx_cfg_h 0x%x", portn, chan, rx_cfg_h.value));