Lines Matching defs:nxgep
52 nxge_test_and_set(p_nxge_t nxgep, uint8_t tas)
57 handle = NXGE_DEV_NPI_HANDLE(nxgep);
67 nxge_set_fzc_multi_part_ctl(p_nxge_t nxgep, boolean_t mpc)
72 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_set_fzc_multi_part_ctl"));
79 if (nxgep->use_partition && nxgep->function_num) {
83 handle = NXGE_DEV_NPI_HANDLE(nxgep);
85 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
90 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_set_fzc_multi_part_ctl"));
96 nxge_get_fzc_multi_part_ctl(p_nxge_t nxgep, boolean_t *mpc_p)
101 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_get_fzc_multi_part_ctl"));
103 handle = NXGE_DEV_NPI_HANDLE(nxgep);
105 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
109 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_get_fzc_multi_part_ctl"));
119 nxge_fzc_intr_init(p_nxge_t nxgep)
123 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_init"));
126 if ((status = nxge_fzc_intr_tmres_set(nxgep)) != NXGE_OK) {
130 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
135 if ((status = nxge_fzc_intr_ldg_num_set(nxgep)) != NXGE_OK)
139 if ((status = nxge_fzc_intr_sid_set(nxgep)) != NXGE_OK)
145 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_init"));
151 nxge_fzc_intr_ldg_num_set(p_nxge_t nxgep)
159 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_ldg_num_set"));
161 if (nxgep->ldgvp == NULL) {
165 ldgp = nxgep->ldgvp->ldgp;
166 ldvp = nxgep->ldgvp->ldvp;
171 handle = NXGE_DEV_NPI_HANDLE(nxgep);
173 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
174 NXGE_DEBUG_MSG((nxgep, INT_CTL,
183 NXGE_DEBUG_MSG((nxgep, INT_CTL,
189 NXGE_DEBUG_MSG((nxgep, INT_CTL,
196 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_ldg_num_set"));
202 nxge_fzc_intr_tmres_set(p_nxge_t nxgep)
207 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_tmrese_set"));
208 if (nxgep->ldgvp == NULL) {
211 handle = NXGE_DEV_NPI_HANDLE(nxgep);
212 if ((rs = npi_fzc_ldg_timer_res_set(handle, nxgep->ldgvp->tmres))) {
215 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_tmrese_set"));
221 nxge_fzc_intr_sid_set(p_nxge_t nxgep)
229 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_sid_set"));
230 if (nxgep->ldgvp == NULL) {
231 NXGE_DEBUG_MSG((nxgep, INT_CTL,
235 handle = NXGE_DEV_NPI_HANDLE(nxgep);
236 ldgp = nxgep->ldgvp->ldgp;
237 NXGE_DEBUG_MSG((nxgep, INT_CTL,
238 "==> nxge_fzc_intr_sid_set: #int %d", nxgep->ldgvp->ldg_intrs));
239 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
244 NXGE_DEBUG_MSG((nxgep, INT_CTL,
250 NXGE_DEBUG_MSG((nxgep, INT_CTL,
257 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_sid_set"));
271 * nxgep
282 nxge_init_fzc_rdc(p_nxge_t nxgep, uint16_t channel)
295 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_tdc"));
297 handle = NXGE_DEV_NPI_HANDLE(nxgep);
302 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
314 page1.func_num = nxgep->function_num;
321 page2.func_num = nxgep->function_num;
326 if (nxgep->niu_type == N2_NIU) {
330 NXGE_DEBUG_MSG((nxgep, RX_CTL,
334 status = nxge_init_fzc_rdc_pages(nxgep, channel,
340 } else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
342 status = nxge_init_fzc_rdc_pages(nxgep, channel,
357 (nxgep->nxge_port_rcr_size - RXDMA_RED_LESS_ENTRIES);
360 (nxgep->nxge_port_rcr_size - RXDMA_RED_LESS_ENTRIES);
362 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
369 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_init_fzc_rdc"));
380 * nxgep
393 nxge_init_fzc_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
400 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_init_fzc_rxdma_channel"));
402 rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel];
403 rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel];
405 if (nxgep->niu_type == N2_NIU) {
408 NXGE_DEBUG_MSG((nxgep, RX_CTL,
412 status = nxge_init_hv_fzc_rxdma_channel_pages(nxgep, channel,
420 NXGE_DEBUG_MSG((nxgep, RX_CTL,
424 status = nxge_init_fzc_rxdma_channel_pages(nxgep, channel,
430 } else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
432 status = nxge_init_fzc_rxdma_channel_pages(nxgep,
442 status = nxge_init_fzc_rxdma_channel_red(nxgep, channel, rcr_ring);
444 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_init_fzc_rxdma_channel"));
457 * nxgep
475 p_nxge_t nxgep,
485 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
489 if (nxgep->niu_type == N2_NIU) {
490 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
496 if (nxgep->niu_type == N2_NIU) {
497 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
506 handle = NXGE_DEV_NPI_HANDLE(nxgep);
533 nxge_init_fzc_rxdma_channel_pages(p_nxge_t nxgep,
540 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
543 handle = NXGE_DEV_NPI_HANDLE(nxgep);
547 cfg.func_num = nxgep->function_num;
581 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
589 nxge_init_fzc_rxdma_channel_red(p_nxge_t nxgep,
596 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rxdma_channel_red"));
598 handle = NXGE_DEV_NPI_HANDLE(nxgep);
605 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
615 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
629 * nxgep
644 nxge_init_fzc_tdc(p_nxge_t nxgep, uint16_t channel)
651 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_tdc"));
659 page1.func_num = nxgep->function_num;
666 page1.func_num = nxgep->function_num;
672 if (nxgep->niu_type == N2_NIU) {
673 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
677 (void) nxge_init_fzc_tdc_pages(nxgep, channel,
681 if (nxgep->niu_type != N2_NIU) {
682 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
684 (void) nxge_init_fzc_tdc_pages(nxgep, channel,
700 handle = NXGE_DEV_NPI_HANDLE(nxgep);
704 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_init_fzc_tdc"));
711 nxge_init_fzc_txdma_channel(p_nxge_t nxgep, uint16_t channel,
716 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
719 if (nxgep->niu_type == N2_NIU) {
722 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
725 status = nxge_init_hv_fzc_txdma_channel_pages(nxgep, channel,
733 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
737 (void) nxge_init_fzc_txdma_channel_pages(nxgep, channel,
740 } else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
742 (void) nxge_init_fzc_txdma_channel_pages(nxgep,
752 (void) nxge_init_fzc_txdma_channel_drr(nxgep, channel, tx_ring_p);
754 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
761 nxge_init_fzc_rx_common(p_nxge_t nxgep)
772 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rx_common"));
773 handle = NXGE_DEV_NPI_HANDLE(nxgep);
775 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
812 hardware = &nxgep->pt_config.hw_config;
814 /* Does this table belong to <nxgep>? */
815 if (hardware->grpids[table] == (nxgep->function_num + 256)) {
816 rdc_grp_p = &nxgep->pt_config.rdc_grps[table];
817 status = nxge_init_fzc_rdc_tbl(nxgep, rdc_grp_p, table);
823 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
968 nxge_init_fzc_rxdma_port(p_nxge_t nxgep)
977 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rxdma_port"));
979 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
981 handle = NXGE_DEV_NPI_HANDLE(nxgep);
987 if ((nxgep->mac.portmode == PORT_1G_COPPER) ||
988 (nxgep->mac.portmode == PORT_1G_FIBER) ||
989 (nxgep->mac.portmode == PORT_1G_TN1010) ||
990 (nxgep->mac.portmode == PORT_1G_SERDES)) {
992 nxgep->function_num, NXGE_RX_DRR_WT_1G);
999 rs = npi_rxdma_cfg_default_port_rdc(handle, nxgep->function_num,
1009 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1021 nxgep->function_num, i, &hostinfo);
1026 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1034 nxge_fzc_dmc_def_port_rdc(p_nxge_t nxgep, uint8_t port, uint16_t rdc)
1037 rs = npi_rxdma_cfg_default_port_rdc(nxgep->npi_reg_handle,
1053 * nxgep
1071 p_nxge_t nxgep,
1081 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1085 if (nxgep->niu_type == N2_NIU) {
1086 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1092 if (nxgep->niu_type == N2_NIU) {
1093 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1102 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1128 nxge_init_fzc_txdma_channel_pages(p_nxge_t nxgep, uint16_t channel,
1135 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1139 if (nxgep->niu_type == N2_NIU) {
1140 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1146 if (nxgep->niu_type == N2_NIU) {
1147 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1156 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1157 cfg.func_num = nxgep->function_num;
1197 nxge_init_fzc_txdma_channel_drr(p_nxge_t nxgep, uint16_t channel,
1203 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1214 nxge_fzc_sys_err_mask_set(p_nxge_t nxgep, uint64_t mask)
1219 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1234 * nxgep
1251 nxge_init_hv_fzc_txdma_channel_pages(p_nxge_t nxgep, uint16_t channel,
1260 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1270 hverr = nxge_init_hv_fzc_lp_op(nxgep, (uint64_t)channel,
1277 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1293 hverr = nxge_init_hv_fzc_lp_op(nxgep, (uint64_t)channel,
1297 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1314 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1327 hverr = nxge_init_hv_fzc_lp_op(nxgep, (uint64_t)channel,
1334 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1347 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1363 hverr = nxge_init_hv_fzc_lp_op(nxgep, (uint64_t)channel,
1367 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1384 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1392 nxge_init_hv_fzc_rxdma_channel_pages(p_nxge_t nxgep,
1401 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1409 hverr = nxge_init_hv_fzc_lp_op(nxgep, (uint64_t)channel,
1416 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1433 hverr = nxge_init_hv_fzc_lp_op(nxgep, (uint64_t)channel,
1437 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1455 hverr = nxge_init_hv_fzc_lp_op(nxgep, (uint64_t)channel,
1462 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1479 hverr = nxge_init_hv_fzc_lp_op(nxgep, (uint64_t)channel,
1483 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1502 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1534 nxge_init_hv_fzc_lp_op(p_nxge_t nxgep, uint64_t channel,
1540 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxgep->nxge_hw_p->hio;
1543 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1546 major = nxgep->niu_hsvc.hsvc_major;
1547 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
1562 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1589 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1596 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1609 hverr = (*io_fp->lp_cfgh_conf)(nxgep->niu_cfg_hdl,
1613 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1620 hverr = (*io_fp->lp_cfgh_info)(nxgep->niu_cfg_hdl,
1629 hverr = (*io_fp->lp_cfgh_conf)(nxgep->niu_cfg_hdl,
1634 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1641 hverr = (*io_fp->lp_cfgh_info)(nxgep->niu_cfg_hdl,
1650 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1661 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1667 NXGE_DEBUG_MSG((nxgep, DMA_CTL,