Lines Matching defs:nxgep
88 nxge_tcam_dump_entry(p_nxge_t nxgep, uint32_t location)
95 handle = nxgep->npi_reg_handle;
101 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
109 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "location %x\n"
121 nxge_get_tcam(p_nxge_t nxgep, p_mblk_t mp)
128 uint32_t stop_location = nxgep->classifier.tcam_size;
132 if ((location >= nxgep->classifier.tcam_size) || (location < -1)) {
133 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
139 stop_location = nxgep->classifier.tcam_size;
145 (void) nxge_tcam_dump_entry(nxgep, tcam_loc);
160 nxge_fflp_vlan_tbl_clear_all(p_nxge_t nxgep)
167 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_vlan_tbl_clear_all "));
168 handle = nxgep->npi_reg_handle;
172 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
178 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_vlan_tbl_clear_all "));
192 nxge_fflp_tcam_init(p_nxge_t nxgep)
199 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_tcam_init"));
200 handle = nxgep->npi_reg_handle;
204 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "failed TCAM Disable\n"));
208 access_ratio = nxgep->param_arr[param_tcam_access_ratio].value;
211 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
222 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
233 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
238 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_tcam_init"));
255 nxge_fflp_tcam_invalidate_all(p_nxge_t nxgep)
260 uint16_t start = 0, stop = nxgep->classifier.tcam_size;
263 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
265 handle = nxgep->npi_reg_handle;
266 if ((hw_p = nxgep->nxge_hw_p) == NULL) {
267 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
269 " common hardware not set", nxgep->niu_type));
277 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
283 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
300 nxge_fflp_fcram_invalidate_all(p_nxge_t nxgep)
319 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_fcram_invalidate_all"));
322 handle = nxgep->npi_reg_handle;
326 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "failed partition cfg\n"));
332 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
346 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
351 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_fcram_invalidate_all"));
356 nxge_fflp_fcram_init(p_nxge_t nxgep)
366 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_fcram_init"));
375 handle = nxgep->npi_reg_handle;
380 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "failed FCRAM Reset. "));
384 access_ratio = nxgep->param_arr[param_fcram_access_ratio].value;
387 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "failed FCRAM Access ratio"
394 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
403 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
410 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_fcram_init"));
415 nxge_logical_mac_assign_rdc_table(p_nxge_t nxgep, uint8_t alt_mac)
422 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
424 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
429 handle = nxgep->npi_reg_handle;
436 nxgep->function_num, alt_mac, &mac_rdc);
439 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
447 nxge_main_mac_assign_rdc_table(p_nxge_t nxgep)
454 handle = nxgep->npi_reg_handle;
456 mac_rdc.bits.w0.rdc_tbl_num = nxgep->class_config.mac_rdcgrp;
458 switch (nxgep->function_num) {
468 nxgep->function_num, XMAC_UNIQUE_HOST_INFO_ENTRY, &mac_rdc);
473 nxgep->function_num, BMAC_UNIQUE_HOST_INFO_ENTRY, &mac_rdc);
476 nxgep->function_num, i, &mac_rdc);
479 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
485 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
497 nxge_alt_mcast_mac_assign_rdc_table(p_nxge_t nxgep)
503 handle = nxgep->npi_reg_handle;
505 mac_rdc.bits.w0.rdc_tbl_num = nxgep->class_config.mcast_rdcgrp;
507 switch (nxgep->function_num) {
511 nxgep->function_num, XMAC_MULTI_HOST_INFO_ENTRY, &mac_rdc);
516 nxgep->function_num, BMAC_MULTI_HOST_INFO_ENTRY, &mac_rdc);
519 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
525 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
533 nxge_fflp_init_hostinfo(p_nxge_t nxgep)
537 status = nxge_alt_mcast_mac_assign_rdc_table(nxgep);
538 status |= nxge_main_mac_assign_rdc_table(nxgep);
543 nxge_fflp_hw_reset(p_nxge_t nxgep)
549 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_hw_reset"));
551 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
552 status = nxge_fflp_fcram_init(nxgep);
554 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
560 status = nxge_fflp_tcam_init(nxgep);
562 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
567 handle = nxgep->npi_reg_handle;
570 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
577 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
585 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
592 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
598 status = nxge_fflp_tcam_invalidate_all(nxgep);
600 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
606 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
607 status = nxge_fflp_fcram_invalidate_all(nxgep);
609 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
616 status = nxge_fflp_vlan_tbl_clear_all(nxgep);
618 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
622 nxgep->classifier.state |= NXGE_FFLP_HW_RESET;
624 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_hw_reset"));
629 nxge_cfg_ip_cls_flow_key(p_nxge_t nxgep, tcam_class_t l3_class,
636 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_cfg_ip_cls_flow_key"));
637 handle = nxgep->npi_reg_handle;
660 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, " nxge_cfg_ip_cls_flow_key"
664 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " <== nxge_cfg_ip_cls_flow_key"));
669 nxge_cfg_ip_cls_flow_key_get(p_nxge_t nxgep, tcam_class_t l3_class,
677 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_cfg_ip_cls_flow_key_get"));
678 handle = nxgep->npi_reg_handle;
683 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, " nxge_cfg_ip_cls_flow_key"
705 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
709 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
715 nxge_cfg_tcam_ip_class_get(p_nxge_t nxgep, tcam_class_t class,
723 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_cfg_tcam_ip_class"));
726 handle = nxgep->npi_reg_handle;
730 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, " nxge_cfg_tcam_ip_class"
741 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
747 nxge_cfg_tcam_ip_class(p_nxge_t nxgep, tcam_class_t class,
755 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_cfg_tcam_ip_class"));
757 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
761 handle = nxgep->npi_reg_handle;
774 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, " nxge_cfg_tcam_ip_class"
782 nxge_fflp_set_hash1(p_nxge_t nxgep, uint32_t h1)
788 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_init_h1"));
789 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
791 handle = nxgep->npi_reg_handle;
794 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
798 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " <== nxge_fflp_init_h1"));
803 nxge_fflp_set_hash2(p_nxge_t nxgep, uint16_t h2)
809 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_init_h2"));
810 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
813 handle = nxgep->npi_reg_handle;
816 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
820 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " <== nxge_fflp_init_h2"));
825 nxge_classify_init_sw(p_nxge_t nxgep)
829 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_classify_init_sw"));
830 classify_ptr = &nxgep->classifier;
833 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
838 classify_ptr->tcam_size = nxgep->nxge_hw_p->tcam_size / nxgep->nports;
839 classify_ptr->tcam_entries = (tcam_flow_spec_t *)nxgep->nxge_hw_p->tcam;
840 classify_ptr->tcam_top = nxgep->function_num;
849 nxgep->classifier.tcam_location = nxgep->function_num;
850 nxgep->classifier.fragment_bug = 1;
853 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_classify_init_sw"));
858 nxge_classify_exit_sw(p_nxge_t nxgep)
860 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_classify_exit_sw"));
861 nxgep->classifier.state = NULL;
862 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_classify_exit_sw"));
878 nxge_get_rdc_group(p_nxge_t nxgep, uint8_t class, uint64_t cookie)
886 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
891 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
899 nxge_get_rdc_offset(p_nxge_t nxgep, uint8_t class, uint64_t cookie)
906 nxge_fill_tcam_entry_udp(p_nxge_t nxgep, flow_spec_t *flow_spec,
933 nxge_fill_tcam_entry_udp_ipv6(p_nxge_t nxgep, flow_spec_t *flow_spec,
942 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
966 nxge_fill_tcam_entry_tcp(p_nxge_t nxgep, flow_spec_t *flow_spec,
993 nxge_fill_tcam_entry_sctp(p_nxge_t nxgep, flow_spec_t *flow_spec,
1019 nxge_fill_tcam_entry_tcp_ipv6(p_nxge_t nxgep, flow_spec_t *flow_spec,
1029 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1052 nxge_fill_tcam_entry_sctp_ipv6(p_nxge_t nxgep, flow_spec_t *flow_spec,
1061 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1086 nxge_fill_tcam_entry_ah_esp(p_nxge_t nxgep, flow_spec_t *flow_spec,
1119 nxge_fill_tcam_entry_ah_esp_ipv6(p_nxge_t nxgep, flow_spec_t *flow_spec,
1129 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1157 nxge_fill_tcam_entry_ip_usr(p_nxge_t nxgep, flow_spec_t *flow_spec,
1188 nxge_flow_get_hash(p_nxge_t nxgep, flow_resource_t *flow_res,
1198 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_flow_get_hash"));
1202 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1242 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_flow_get_hash"));
1247 nxge_add_fcram_entry(p_nxge_t nxgep, flow_resource_t *flow_res)
1253 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_add_fcram_entry"));
1254 status = nxge_flow_get_hash(nxgep, flow_res, &H1, &H2);
1256 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1261 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_add_fcram_entry"));
1270 nxge_add_tcam_entry(p_nxge_t nxgep, flow_resource_t *flow_res)
1283 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_add_tcam_entry"));
1284 handle = nxgep->npi_reg_handle;
1290 location = (tcam_location_t)nxge_tcam_get_index(nxgep,
1293 if ((hw_p = nxgep->nxge_hw_p) == NULL) {
1294 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1296 nxgep->niu_type));
1383 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1393 nxge_fill_tcam_entry_tcp(nxgep, flow_spec, &tcam_ptr);
1394 rdc_grp = nxge_get_rdc_group(nxgep, TCAM_CLASS_TCP_IPV4,
1396 offset = nxge_get_rdc_offset(nxgep, TCAM_CLASS_TCP_IPV4,
1401 nxge_fill_tcam_entry_udp(nxgep, flow_spec, &tcam_ptr);
1402 rdc_grp = nxge_get_rdc_group(nxgep,
1405 offset = nxge_get_rdc_offset(nxgep,
1411 nxge_fill_tcam_entry_tcp_ipv6(nxgep,
1413 rdc_grp = nxge_get_rdc_group(nxgep, TCAM_CLASS_TCP_IPV6,
1415 offset = nxge_get_rdc_offset(nxgep, TCAM_CLASS_TCP_IPV6,
1420 nxge_fill_tcam_entry_udp_ipv6(nxgep,
1422 rdc_grp = nxge_get_rdc_group(nxgep,
1425 offset = nxge_get_rdc_offset(nxgep,
1431 nxge_fill_tcam_entry_sctp(nxgep, flow_spec, &tcam_ptr);
1432 rdc_grp = nxge_get_rdc_group(nxgep,
1435 offset = nxge_get_rdc_offset(nxgep,
1441 nxge_fill_tcam_entry_sctp_ipv6(nxgep,
1443 rdc_grp = nxge_get_rdc_group(nxgep,
1446 offset = nxge_get_rdc_offset(nxgep,
1453 nxge_fill_tcam_entry_ah_esp(nxgep, flow_spec, &tcam_ptr);
1454 rdc_grp = nxge_get_rdc_group(nxgep,
1457 offset = nxge_get_rdc_offset(nxgep,
1464 nxge_fill_tcam_entry_ah_esp_ipv6(nxgep,
1466 rdc_grp = nxge_get_rdc_group(nxgep,
1469 offset = nxge_get_rdc_offset(nxgep,
1475 nxge_fill_tcam_entry_ip_usr(nxgep, flow_spec, &tcam_ptr,
1477 rdc_grp = nxge_get_rdc_group(nxgep,
1479 offset = nxge_get_rdc_offset(nxgep,
1483 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1489 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1497 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1513 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1519 (void *) &nxgep->classifier.tcam_entries[location].tce,
1521 nxgep->classifier.tcam_entry_cnt++;
1522 nxgep->classifier.tcam_entries[location].valid = 1;
1525 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_add_tcam_entry"));
1529 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_add_tcam_entry FAILED"));
1534 nxge_tcam_handle_ip_fragment(p_nxge_t nxgep)
1545 handle = nxgep->npi_reg_handle;
1550 location = nxgep->function_num;
1551 nxgep->classifier.fragment_bug_location = location;
1553 if ((hw_p = nxgep->nxge_hw_p) == NULL) {
1554 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1556 nxgep->niu_type));
1565 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1571 tcam_ptr.match_action.bits.ldw.rdctbl = nxgep->class_config.mac_rdcgrp;
1580 NXGE_DEBUG_MSG((nxgep,
1588 (void *) &nxgep->classifier.tcam_entries[location].tce,
1590 nxgep->classifier.tcam_entry_cnt++;
1591 nxgep->classifier.tcam_entries[location].valid = 1;
1594 class_config = nxgep->class_config.class_cfg[class];
1596 status = nxge_fflp_ip_class_config(nxgep, class, class_config);
1600 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1611 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1622 nxge_flow_need_hash_lookup(p_nxge_t nxgep, flow_resource_t *flow_res)
1628 nxge_add_flow(p_nxge_t nxgep, flow_resource_t *flow_res)
1634 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1636 insert_hash = nxge_flow_need_hash_lookup(nxgep, flow_res);
1639 status = nxge_add_fcram_entry(nxgep, flow_res);
1641 status = nxge_add_tcam_entry(nxgep, flow_res);
1647 nxge_put_tcam(p_nxge_t nxgep, p_mblk_t mp)
1652 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1655 (void) nxge_add_tcam_entry(nxgep, fs);
1659 nxge_fflp_config_tcam_enable(p_nxge_t nxgep)
1661 npi_handle_t handle = nxgep->npi_reg_handle;
1664 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_config_tcam_enable"));
1667 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1671 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " <== nxge_fflp_config_tcam_enable"));
1676 nxge_fflp_config_tcam_disable(p_nxge_t nxgep)
1678 npi_handle_t handle = nxgep->npi_reg_handle;
1681 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1685 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1689 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1695 nxge_fflp_config_hash_lookup_enable(p_nxge_t nxgep)
1697 npi_handle_t handle = nxgep->npi_reg_handle;
1703 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1705 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1713 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1722 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1728 nxge_fflp_config_hash_lookup_disable(p_nxge_t nxgep)
1730 npi_handle_t handle = nxgep->npi_reg_handle;
1736 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1738 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1746 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1755 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1761 nxge_fflp_config_llc_snap_enable(p_nxge_t nxgep)
1763 npi_handle_t handle = nxgep->npi_reg_handle;
1766 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1770 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1774 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1780 nxge_fflp_config_llc_snap_disable(p_nxge_t nxgep)
1782 npi_handle_t handle = nxgep->npi_reg_handle;
1785 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1789 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1793 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1799 nxge_fflp_ip_usr_class_config(p_nxge_t nxgep, tcam_class_t class,
1803 npi_handle_t handle = nxgep->npi_reg_handle;
1807 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_ip_usr_class_config"));
1822 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1833 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1838 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_ip_usr_class_config"));
1843 nxge_fflp_ip_class_config(p_nxge_t nxgep, tcam_class_t class, uint32_t config)
1850 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_ip_class_config"));
1852 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1860 t_status = nxge_cfg_tcam_ip_class(nxgep, class, class_config);
1861 f_status = nxge_cfg_ip_cls_flow_key(nxgep, class, class_config);
1864 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1870 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1875 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_ip_class_config"));
1880 nxge_fflp_ip_class_config_get(p_nxge_t nxgep, tcam_class_t class,
1887 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, " ==> nxge_fflp_ip_class_config"));
1890 t_status = nxge_cfg_tcam_ip_class_get(nxgep, class, &t_class_config);
1891 f_status = nxge_cfg_ip_cls_flow_key_get(nxgep, class, &f_class_config);
1894 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1901 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1907 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
1912 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_ip_class_config_get"));
1917 nxge_fflp_ip_class_config_all(p_nxge_t nxgep)
1926 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_ip_class_config"));
1929 class_config = nxgep->class_config.class_cfg[class];
1931 (void) nxge_fflp_ip_class_config(nxgep, class, class_config);
1933 status = nxge_fflp_ip_class_config(nxgep, class, class_config);
1935 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1942 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_ip_class_config"));
1947 nxge_fflp_config_vlan_table(p_nxge_t nxgep, uint16_t vlan_id)
1957 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_config_vlan_table"));
1958 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1959 handle = nxgep->npi_reg_handle;
1961 port = nxgep->function_num;
1964 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1970 if ((hw_p = nxgep->nxge_hw_p) == NULL) {
1971 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1973 " common hardware not set", nxgep->niu_type));
1984 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1991 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_fflp_config_vlan_table"));
1996 nxge_fflp_update_hw(p_nxge_t nxgep)
2011 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_fflp_update_hw"));
2013 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2014 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2017 status = nxge_fflp_set_hash1(nxgep, p_class_cfgp->init_h1);
2019 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
2024 status = nxge_fflp_set_hash2(nxgep, p_class_cfgp->init_h2);
2026 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
2033 pa = (p_nxge_param_t)&nxgep->param_arr[param_vlan_2rdc_grp];
2045 status = nxge_fflp_config_vlan_table(nxgep,
2048 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
2057 pa = (p_nxge_param_t)&nxgep->param_arr[param_mac_2rdc_grp];
2066 status = nxge_logical_mac_assign_rdc_table(nxgep,
2069 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
2079 status = nxge_fflp_ip_class_config_all(nxgep);
2081 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2089 nxge_classify_init_hw(p_nxge_t nxgep)
2093 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "==> nxge_classify_init_hw"));
2095 if (nxgep->classifier.state & NXGE_FFLP_HW_INIT) {
2096 NXGE_DEBUG_MSG((nxgep, FFLP_CTL,
2102 status = nxge_fflp_update_hw(nxgep);
2104 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2111 status = nxge_main_mac_assign_rdc_table(nxgep);
2113 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2118 status = nxge_alt_mcast_mac_assign_rdc_table(nxgep);
2120 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2125 if (nxgep->classifier.fragment_bug == 1) {
2126 status = nxge_tcam_handle_ip_fragment(nxgep);
2128 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2134 nxgep->classifier.state |= NXGE_FFLP_HW_INIT;
2135 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_classify_init_hw"));
2140 nxge_fflp_handle_sys_errors(p_nxge_t nxgep)
2153 handle = nxgep->npi_handle;
2154 statsp = (p_nxge_fflp_stats_t)&nxgep->statsp->fflp_stats;
2155 portn = nxgep->mac.portnum;
2165 NXGE_ERROR_MSG((nxgep, FFLP_CTL,
2173 NXGE_ERROR_MSG((nxgep, FFLP_CTL,
2178 NXGE_FM_REPORT_ERROR(nxgep, NULL, NULL,
2185 NXGE_ERROR_MSG((nxgep, FFLP_CTL,
2192 NXGE_ERROR_MSG((nxgep, FFLP_CTL,
2201 NXGE_ERROR_MSG((nxgep, FFLP_CTL,
2204 NXGE_ERROR_MSG((nxgep, FFLP_CTL,
2209 NXGE_FM_REPORT_ERROR(nxgep, NULL, NULL,
2214 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2221 NXGE_ERROR_MSG((nxgep, FFLP_CTL,
2231 NXGE_FM_REPORT_ERROR(nxgep, NULL, NULL,
2251 NXGE_ERROR_MSG((nxgep, FFLP_CTL,
2258 NXGE_FM_REPORT_ERROR(nxgep, NULL, NULL,
2267 nxge_get_valid_tcam_cnt(p_nxge_t nxgep) {
2268 return ((nxgep->classifier.fragment_bug == 1) ?
2269 nxgep->classifier.tcam_entry_cnt - 1 :
2270 nxgep->classifier.tcam_entry_cnt);
2274 nxge_rxdma_channel_cnt(p_nxge_t nxgep)
2279 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2286 nxge_rxclass_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp)
2291 if (nxgep == NULL) {
2300 cfg_info->data = nxge_rxdma_channel_cnt(nxgep);
2303 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_tcam_lock);
2304 cfg_info->rule_cnt = nxge_get_valid_tcam_cnt(nxgep);
2305 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_tcam_lock);
2308 nxge_get_tcam_entry(nxgep, &cfg_info->fs);
2311 nxge_get_tcam_entry_all(nxgep, cfg_info);
2314 nxge_del_tcam_entry(nxgep, cfg_info->fs.location);
2317 (void) nxge_add_tcam_entry(nxgep, &cfg_info->fs);
2324 nxge_rxhash_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp)
2329 if (nxgep == NULL) {
2338 nxge_add_iptun_class(nxgep, &cfg_info->iptun_cfg,
2342 nxge_cfg_iptun_hash(nxgep, &cfg_info->iptun_cfg,
2346 nxge_del_iptun_class(nxgep, cfg_info->class_id);
2349 nxge_get_iptun_class(nxgep, &cfg_info->iptun_cfg,
2353 nxge_set_ip_cls_sym(nxgep, cfg_info->class_id, cfg_info->sym);
2356 nxge_get_ip_cls_sym(nxgep, cfg_info->class_id, &cfg_info->sym);
2363 nxge_get_tcam_entry_all(p_nxge_t nxgep, rx_class_cfg_t *cfgp)
2365 nxge_classify_t *clasp = &nxgep->classifier;
2371 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_tcam_lock);
2375 k = nxge_tcam_get_index(nxgep, j);
2382 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_tcam_lock);
2386 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_get_tcam_entry_all"
2394 nxge_tcam_get_index(p_nxge_t nxgep, uint16_t index)
2397 if (index >= (nxgep->classifier.tcam_size - 1))
2399 if (nxgep->classifier.fragment_bug == 1)
2401 return (nxgep->classifier.tcam_top + (index * nxgep->nports));
2437 nxge_get_tcam_entry(p_nxge_t nxgep, flow_resource_t *fs)
2446 index = nxge_tcam_get_index(nxgep, (uint16_t)fs->location);
2447 tcam_ep = &nxgep->classifier.tcam_entries[index];
2449 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_get_tcam_entry: :"
2518 nxge_del_tcam_entry(p_nxge_t nxgep, uint32_t location)
2526 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_tcam_lock);
2527 index = nxge_tcam_get_index(nxgep, (uint16_t)location);
2528 tcam_ep = &nxgep->classifier.tcam_entries[index];
2530 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_del_tcam_entry: :"
2541 p_nxge_hw_list_t hw_p = nxgep->nxge_hw_p;
2553 nxgep->npi_reg_handle,
2565 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2572 rs = npi_fflp_tcam_entry_invalidate(nxgep->npi_reg_handle, index);
2574 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2580 nxgep->classifier.tcam_entries[index].valid = 0;
2581 nxgep->classifier.tcam_entry_cnt--;
2583 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_tcam_lock);
2584 NXGE_DEBUG_MSG((nxgep, FFLP_CTL, "<== nxge_del_tcam_entry"));
2587 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_tcam_lock);
2588 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2621 nxge_set_iptun_usr_cls_reg(p_nxge_t nxgep, uint64_t class,
2624 npi_handle_t handle = nxgep->npi_reg_handle;
2651 nxge_add_iptun_class(p_nxge_t nxgep, iptun_cfg_t *iptunp,
2657 p_nxge_hw_list_t hw_p = nxgep->nxge_hw_p;
2658 npi_handle_t handle = nxgep->npi_reg_handle;
2693 rs = nxge_set_iptun_usr_cls_reg(nxgep, class, iptunp);
2716 rs = nxge_set_iptun_usr_cls_reg(nxgep, class,
2731 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2742 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2748 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_add_iptun_class: FAILED"));
2752 nxge_is_iptun_cls_present(p_nxge_t nxgep, uint8_t cls_id, int *idx)
2755 p_nxge_hw_list_t hw_p = nxgep->nxge_hw_p;
2768 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2778 nxge_cfg_iptun_hash(p_nxge_t nxgep, iptun_cfg_t *iptunp, uint8_t cls_id)
2781 npi_handle_t handle = nxgep->npi_reg_handle;
2785 if (!nxge_is_iptun_cls_present(nxgep, cls_id, &idx)) {
2786 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2821 nxge_del_iptun_class(p_nxge_t nxgep, uint8_t cls_id)
2824 npi_handle_t handle = nxgep->npi_reg_handle;
2829 if (!nxge_is_iptun_cls_present(nxgep, cls_id, &i)) {
2830 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2835 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_tcam_lock);
2839 nxgep->nxge_hw_p->tcam_l3_prog_cls[i].flow_pkt_type = 0;
2840 if (nxgep->nxge_hw_p->tcam_l3_prog_cls[i].tcam_ref_cnt == 0)
2841 nxgep->nxge_hw_p->tcam_l3_prog_cls[i].valid = 0;
2843 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_tcam_lock);
2846 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_tcam_lock);
2847 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_del_iptun_class: FAILED"));
2851 nxge_get_iptun_class(p_nxge_t nxgep, iptun_cfg_t *iptunp, uint8_t cls_id)
2855 npi_handle_t handle = nxgep->npi_reg_handle;
2861 if (!nxge_is_iptun_cls_present(nxgep, cls_id, &i))
2866 pid = nxgep->nxge_hw_p->tcam_l3_prog_cls[i].pid;
2913 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_get_iptun_class: FAILED"));
2917 nxge_set_ip_cls_sym(p_nxge_t nxgep, uint8_t cls_id, uint8_t sym)
2919 npi_handle_t handle = nxgep->npi_reg_handle;
2926 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2931 nxge_get_ip_cls_sym(p_nxge_t nxgep, uint8_t cls_id, uint8_t *sym)
2933 npi_handle_t handle = nxgep->npi_reg_handle;
2948 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_get_ip_cls_sym: FAILED"));