Cross Reference: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi

Lines Matching refs:value
132 	uint64_t		value, offset;
151 		TXDMA_REG_READ64(handle, tdc_dmc_offset[i], tdc, &value);
157 		    value));
183 	uint64_t value;
192 		NXGE_REG_RD64(handle, (uint32_t)tx_fzc_offset[i], &value);
194 		NXGE_REG_RD64(handle, tx_fzc_offset[i], &value);
199 		    tx_fzc_name[i], value));
210 	uint64_t		value;
227 	value = 0;
229 		TXDMA_REG_WRITE64(handle, tdc_dmc_offset[i], tdc, value);
262 	mode32.value = 0;
268 	NXGE_REG_WR64(handle, TX_ADDR_MD_REG, mode32.value);
276  *	(valid bit, mask, value, relocation).
283  *				- value
321 	vld.value = 0;
325 	vld.value |= val;
327 	vld.value = 0;
334 		    channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
341 		    channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
347 	    vld.value | (cfgp->valid << cfgp->page_num));
350 	    "\n==> npi_txdma_log_page_set: vld value "
352 	    vld.value,
369  *	(valid bit, mask, value, relocation).
376  *				- value
405 	vld.value = 0;
410 	    "\n==> npi_txdma_log_page_get: read value "
411 	    " function %d  value 0x%llx\n",
414 	vld.value |= val;
421 		cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
429 		cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
475 	    channel, hdl_p->value);
484  *	valid bit, mask, value, relocation).
546 				cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
550 				cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
582 			cfgp->value = cfgp->reloc = 0;
604 				    (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
608 				    (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
686 		    &vld_p->value);
691 		    channel, vld_p->value);
696 		    &vld.value);
698 		    channel, vld.value | vld_p->value);
936 		cs.value = 0;
937 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
939 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
943 		cs.value = 0;
944 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
952 		cs.value = 0;
954 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
959 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
961 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
966 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
968 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
979 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
980 		cs.value |= ~TX_CS_STOP_N_GO_MASK;
981 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
986 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
988 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
996 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
998 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
1053 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs_p->value);
1057 		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs_p->value);
1061 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
1063 		    cs_p->value | txcs.value);
1119 		    &mask_p->value);
1124 		    mask_p->value);
1128 		TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &mask.value);
1130 		    mask_p->value | mask.value);
1172 	uint64_t	value;
1196 		TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &value);
1198 		    configuration | value);
1329 	cfg.value = ((start_addr & TX_RNG_CFIG_ADDR_MASK) |
1331 	TXDMA_REG_WRITE64(handle, TX_RNG_CFIG_REG, channel, cfg.value);
1434 	mh.value = ml.value = 0;
1438 		TXDMA_REG_READ64(handle, TXDMA_MBH_REG, channel, &mh.value);
1439 		TXDMA_REG_READ64(handle, TXDMA_MBL_REG, channel, &ml.value);
1440 		*mbox_addr = ml.value;
1441 		*mbox_addr |= (mh.value << TXDMA_MBH_ADDR_SHIFT);
1448 		TXDMA_REG_WRITE64(handle, TXDMA_MBL_REG, channel, ml.value);
1451 		TXDMA_REG_WRITE64(handle, TXDMA_MBH_REG, channel, mh.value);
1532 	NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
1564 	NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
1582 	NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
1600 	NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
1678 	kick.value = 0;
1683 	TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, channel, kick.value);
1724 	TXDMA_REG_READ64(handle, TX_RING_KICK_REG, channel, &kick_p->value);
1764 	TXDMA_REG_READ64(handle, TX_RING_HDL_REG, channel, &hdl_p->value);
1795 	TXDMA_REG_READ64(handle, TX_DMA_PRE_ST_REG, channel, &prep->value);
1817 	logh.value = 0;
1818 	TXDMA_REG_READ64(handle, TX_RNG_ERR_LOGH_REG, channel, &logh.value);
1819 	TXDMA_REG_READ64(handle, TX_RNG_ERR_LOGL_REG, channel, &logl.value);
1842 	inj.value = 0;
1844 	NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value);
1854 	inj.value = 0;
1855 	NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
1856 	inj.value |= (err_bits & TDMC_INJ_PAR_ERR_MASK);
1857 	NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value);
1867 	inj.value = 0;
1868 	NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
1869 	*err_bits = (inj.value & TDMC_INJ_PAR_ERR_MASK);
1879 	dbg.value = 0;
1882 	NXGE_REG_WR64(handle, TDMC_DBG_SEL_REG, dbg.value);
1892 	vec.value = 0;
1895 	NXGE_REG_WR64(handle, TDMC_TRAINING_REG, vec.value);
1928 	desc.value = 0;
1930 	desp->value = NXGE_MEM_PIO_READ64(handle);
1932 	sad = (desp->value & TX_PKT_DESC_SAD_MASK);
1933 	xfer_len = ((desp->value & TX_PKT_DESC_TR_LEN_MASK) >>
1936 	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, "\n\t: value 0x%llx\n"
1938 	    desp->value,
1958 	    "\n\t: value 0x%llx\n"
1962 	    hdrp->value,
1993 	TXDMA_REG_WRITE64(handle, TDMC_INTR_DBG_REG, channel, erp->value);
2010 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
2020 		    "cleared to 0 txcs.bits 0x%llx", txcs.value));
2034 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
2044 		    "set to 1 txcs.bits 0x%llx", txcs.value));
2059 		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
2069 		    "set to 0 txcs.bits 0x%llx", txcs.value));